Detection of gate-oxide defects with timing tests at reduced power supply

Retraction:Reliability assurance in early-life-failure test through improved nearest neighbor regression

“…Indeed, the line between marginal defect and process variation defect can already sometimes seem arbitrary [20]. Given all of these challenges, it should come as no surprise that defects due to small variations in placement, alignment and the shaping of complex features are on the rise [21]. Such lithography-based defects often occur within the boundaries of typical logic gates and standard cell libraries, at the level of transistor gate features and lower level interconnect, where geometries are smallest and lithography is most challenging, such defects often cause subtle parametric variations in circuit behavior [22].…”

Identifying Resistive Open Defects in Embedded Cells under Variations

“…Physical weak defects such as resistive open, resistive bridge, and gate-oxide pinhole are considered as important sources of Early Life Failure (ELF), which appear as delay faults [20]. Delay test has been used to detect physical weak defects in a chip, e.g., [5,10,12,15,[21][22][23].…”

“…Delay fault testing and the impact of operating conditions such as supply voltage have been investigated thoroughly in the past. It has been shown that reducing the supply voltage increases the transistor channel resistance, which results in an increasing electrical impact of a gate-drain (or gatesource) resistive bridge defect, or a drain (or source) resistive open defect [10]. Circuit test under varying operating conditions has been studied in many works such as [24,25], which investigate the effect of supply voltage on the circuit delay and delay testing.…”

“…Since they may evolve rather early in the circuits lifetime and turn into catastrophic faults, they have to be covered during the test of high-quality systems [4,5,6]. It is well known that testing at varying voltages and especially low voltage testing increase the fault coverage significantly [7,8,9,10], and modern systems with Adaptive Voltage Frequency Scaling (AVFS) have all the means to support this test strategy [11]. However, technology scaling comes with the additional difficulty that circuits are subject to process variations, which similarly affect the timing as SDFs do.…”

“…Yet, a slow circuit due to variations may be safe whereas a slow circuit due to resistive weak defects may form a reliability threat. Distinguishing cells slow due to variations from defective cells has been the subject of ongoing research [10,[12][13][14] and [15]. A severe limitation of the previous works comes with the fact, that the defective cells are subject to variations too.…”