Detailed routing by sparse grid graph and minimum-area-captured path search

Chen, Gengjie; Pui, Chak-Wa; Chen, Jingsong; Jiang, Bentian; Young, Evangeline F. Y.

doi:10.1145/3287624.3287678

Cited by 23 publications

(6 citation statements)

References 21 publications

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“…Thus, Equations (3) and (4) respectively compute the coordinates of line front and line end of a shape on Layer I by checking the leftmost/lowermost shape and rightmost/uppermost shape on Layers I + 1 and I -1. The index max_j of the rightmost/uppermost track on which a shape of Layer I is placed can be derived by Equation ( 6). Since the arg max can not be directly solved by the ILP solver, we transform Equation ( 6) into Equations (8) and (9).…”

Section: Ilp Constraintsmentioning

confidence: 99%

“…The index max_j of the rightmost/uppermost track on which a shape of Layer I is placed can be derived by Equation ( 6). Since the arg max can not be directly solved by the ILP solver, we transform Equation ( 6) into Equations (8) and (9). is_max(~) is a Boolean variable, which is one if~ is the rightmost/uppermost track occupied by a shape on Layer I, which can be judged by checking tf is occupied by a shape and the tracks on the right/top of tf are all empty.…”

Section: Ilp Constraintsmentioning

confidence: 99%

“…Algorithm 2 demonstrates the backward trace step to get the optimal MSV design solution, the edge with the smallest cost connected to the pseudo sink node is found first (Line 1), and the corresponding placement configuration will be used for the highest layer (Line 2). Lines [3][4][5][6][7][8] utilize the prev function to iteratively derive the placement configuration on the lower adjacent layer, and the optimal MSV design can be constructed from the highest layer to the lowest layer.…”

Section: Graph Optimization Problem Of Msvmentioning

confidence: 99%

“…There have been some existing studies considering complicated design rules in advanced processes. [5] and [6] propose heuristic algorithms to tackle the minimum area and spacing rules and take several iterations of rip-up and re-routing to reduce the number ofDRVs. In addition, there are also some previous works devoting themselves to modeling the design rules into the constraints of integer linear programming (ILP) formulations [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Meshed stack via design considering complicated design rules with automatic constraint generation

Yang

Fang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Ilp Constraintsmentioning

confidence: 99%

Section: Ilp Constraintsmentioning

confidence: 99%

Section: Graph Optimization Problem Of Msvmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Meshed stack via design considering complicated design rules with automatic constraint generation

Yang

Fang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…Maze routing is a classic and efficient routing strategy widely used in routers [22][23][24]. Although it is time consuming compared to other routing methods, the result quality is good due to its optimality for two-pin net.…”

Section: Routability Verificationmentioning

confidence: 99%

Device Layer-Aware Analytical Placement for Analog Circuits

Xu¹,

Li²,

Pui

et al. 2019

Proceedings of the 2019 International Symposium on Physical Design

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The layouts of analog/mixed-signal (AMS) integrated circuits (ICs) are dramatically different from their digital counterparts. AMS circuit layouts usually include a variety of devices, including transistors, capacitors, resistors, and inductors. A complicated AMS IC system with hierarchical structure may also consist of pre-laid out subcircuits. Different types of devices can occupy different manufacturing layers. Therefore, during the layout stage, the devices require co-optimization to achieve high circuit performance. Leveraging the fact that some devices can be built by mutually exclusive layers, they can be carefully designed to overlap each other to effectively reduce the total area and wirelength without degrading the circuit performance. In this paper, we propose an analytical framework to tackle the device layer-aware analog placement problem. Experimental results show that on average the proposed techniques can reduce the total area and half-perimeter wirelength by 9% and 23%, respectively. To verify the routability of the placement results, we also develop an analog global router, which demonstrates that the device layer-aware placement can achieve 18% shorter wirelength during global routing.

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