Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI

Heo, Sun ik; Kahng, Andrew B.; Kim, Min‐Soo; Wang, Lutong; Chutong, Yang,

doi:10.23919/date.2019.8715096

Cited by 17 publications

(4 citation statements)

References 5 publications

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“…The objective function is minimizing the maximum displacement of all cells. Constraint (8) restricts that any two cells cannot overlap with each other if they are in the same row ( is either to the right or left to ). Constraint (9) specifies the boundary of each row.…”

Section: Ilp-based Legalization (Horizontal Movement)mentioning

confidence: 99%

“…Hence, the trained model cannot be directly used when the IR-drop of an individual cell is queried during ECO. We summarize recent IR-drop optimization works [4,[8][9][10] in Table 2. Heo et al propose a dynamic programming method to maximize power staple insertion at post-placement in [8].…”

Section: Introductionmentioning

confidence: 99%

“…We summarize recent IR-drop optimization works [4,[8][9][10] in Table 2. Heo et al propose a dynamic programming method to maximize power staple insertion at post-placement in [8]. To decrease the resistance of the PG network, these inserted short metal pieces connect adjacent PG rails but compete in routing resources with signal nets at low metal layers.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Dynamic IR-drop ECO optimization by cell movement with current waveform staggering and machine learning guidance

Huang

Chen

Wang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Ilp-based Legalization (Horizontal Movement)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Dynamic IR-drop ECO optimization by cell movement with current waveform staggering and machine learning guidance

Huang

Chen

Wang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…Dey et al [3] have done power grid design considering IR drop and EM reliability constraints. Heo et al [4] have done IR drop mitigation by inserting power staple. All the methods mentioned above suffer from large convergence time.…”

Section: B Related Work 1) Conventional Approaches In Powermentioning

confidence: 99%

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning

Dey,

Nandi,

Trivedi

2020

Preprint

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With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and training dataset is generated from the floorplans of some of the power grid designs extracted from IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (∼2%). The proposed DLbased approach also improves the design cycle time with a speedup of ∼6× for standard power grid benchmarks.

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Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node

Jeong,

Shin,

Lee

et al. 2024

IEEE Access

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Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI

Cited by 17 publications

References 5 publications

Dynamic IR-drop ECO optimization by cell movement with current waveform staggering and machine learning guidance

Dynamic IR-drop ECO optimization by cell movement with current waveform staggering and machine learning guidance

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node

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