Detailed Electrical and Reliability Study of Tapered TSVs

Lu, Tiantao; Srivastava, Ankur

doi:10.1201/b19225-3

Cited by 2 publications

(6 citation statements)

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“…Much of our previous finite-element method (FEM)-based simulation work on tapered TSVs dc distribution trend can be found in [9]. However, FEM requires high simulation time, thus it is not applicable for optimization problems in this brief.…”

Section: Tapered Tsv Current Distribution Modelmentioning

confidence: 96%

“…To capture the high degree of current variance in tapered TSV (see [9] for detail), the horizontal planes would require a very 1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.…”

Section: Tapered Tsv Current Distribution Modelmentioning

confidence: 99%

“…The TSV tapering effect is a natural result of the deep reactive ion etching (DRIE)-based TSV manufacturing process. The TSV tapering, even at a very small tapering angle, significantly changes TSVs electrical (i.e., delay in digital circuit) and reliability (i.e., peak current, thermal mechanical stress, and electromigration) [9] properties. This brief quantifies and models the impact of TSV tapering on peak current density as well as develops delay optimizations that account for TSV tapering.…”

Section: Introductionmentioning

confidence: 99%

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Modeling and Layout Optimization for Tapered TSVs

Srivastava

2015

IEEE Trans. VLSI Syst.

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Through-silicon-via (TSV) offers vertical connections for 3-D ICs. Due to its large dimensions and nonideal etching process, TSVs layout needs to be carefully optimized to balance peak current density and delay for digital circuit. This brief investigates the TSVs tapering effect (which is an inevitable byproduct of deep reactive Ion etchingbased manufacturing) and its impact on the TSVs electrical properties. We show that the current crowding effect is more severe in realistic tapered TSVs than ideal cylindrical TSVs. We propose a nonuniform current density model for tapered TSVs, which achieves considerable accuracy and speedup in estimating the current density distribution, when compared with the existing models developed for cylindrical TSVs. We apply our model to perform a detailed study on: 1) impact of TSVs tapering on peak current density and 2) wire sizing problem to minimize TSV-involved path delay under second-order delay model while keeping the peak current density within tolerable levels. A new dynamic programming-based heuristic is proposed to find the optimal wire configuration, which reduces both peak current density and delay, thereby improving the reliability and performance.

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Section: Tapered Tsv Current Distribution Modelmentioning

confidence: 96%

Section: Tapered Tsv Current Distribution Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Modeling and Layout Optimization for Tapered TSVs

Srivastava

2015

IEEE Trans. VLSI Syst.

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“…(12) where Ti,j is the temperature at the grid (i, j), which is a constant value when assuming the logic gate's placement is fixed. Therefore, the stress value, σ (i,j) , calculated by Eqn.11, is a function w.r.t.…”

Section: Tsv Placement Enginementioning

confidence: 99%

“…Recently researchers have used the following time-dependent multi-physics mass transportation equations to represent the physics of TSV's EM [19,4,14,20,18,15,12].…”

Section: Tsv's Em Physicsmentioning

confidence: 99%

Electromigration-aware placement for 3D-ICs

Yang

Srivastava

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSV's EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSV's EM is mutually influenced by neighboring TSVs (due to TSV EM's dependence on TSV-induced thermal mechanical stress) and strongly affected by temperature, iterative optimizations are performed to obtain the optimal TSV's distribution and a desired TSV's temperature. Finally using a compact thermal model and simulated annealing, all logic gates are placed such that the desired temperature profile is reached. Results show that compared with a conventional wirelength centered 3D placer, our design achieves 3.41x longer mean-time-to-failure (MTTF), with only 3% wirelength overhead.

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Detailed Electrical and Reliability Study of Tapered TSVs

Cited by 2 publications

References 0 publications

Modeling and Layout Optimization for Tapered TSVs

Modeling and Layout Optimization for Tapered TSVs

Electromigration-aware placement for 3D-ICs

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