DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level

Rethinagiri, Santhosh Kumar; Palomar, Oscar; Cristal, Adrián; Unsal, Osman S.; Swift, Michael M.

doi:10.1109/socc.2014.6948898

Cited by 6 publications

(5 citation statements)

References 11 publications

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“…Then, the cost functions described in Eqs. (4) and (6) are used with an LSR algorithm to extract time cost parameters and energy cost parameters. These functions will be used to explore the design space.…”

Section: Exploration Resultsmentioning

confidence: 99%

“…The exploration problem is multi-objective as it focuses on optimizing performance, power, and cost and is solved using both tracedriven co-simulations and a genetic solver. More recently, new frameworks have been proposed [3], [4], [5]. They mainly rely on high-level simulations combined with power model to estimate the consumed energy.…”

Section: Related Workmentioning

confidence: 99%

“…DSE was already addressed by a large set of studies. Earlier works have introduced accurate tools based on simulation techniques, e.g., [2], [3], [4], [5]. However with the advent of the many-core era and the explosion of the design space size, the simulation-based approach is no longer an efficient solution.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

Roux

Gautier

Sentieys

et al. 2020

Microprocessors and Microsystems

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Programming heterogeneous multiprocessor architectures combining multiple processor cores and hardware accelerators is a real challenge. Computer-aided design and development tools try to reduce the large design space by simplifying hardware-software mapping mechanisms. However, energy consumption is not well supported in most of design space exploration methodologies due to the difficulty to estimate energy consumption fast and accurately. To this aim, this paper proposes and validates an exploration method for partitioning tilling-based parallel applications on software cores and hardware accelerators under energy-efficiency constraints. The methodology is based on energy and performance measurement of a tiny subset of the design space and an analytical formulation of the performance and energy of an application kernel mapped onto a heterogeneous architecture. This closedform expression is captured and solved using Mixed Integer Linear Programming, which allows for very fast exploration and results in the best hardware and software partitioning under energy constraint. The approach is validated on two application kernels using a Zynq-based architecture showing more than 12% acceleration speed-up and energy saving compared to standard approaches. Results also show that the most energy-efficient solution is application-and platform-dependent and moreover hardly predictable, which highlights the need for fast exploration tools as in this paper.

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Section: Exploration Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

Roux

Gautier

Sentieys

et al. 2020

Microprocessors and Microsystems

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show abstract

“…The processor architecture which we use in this project for heterogeneous computing are DSP C64x [22], GPU Tegra3 [10], FPGA Xilinx Zynq 6951910 and Multi-core Cortex-A9 [23]. All the cores/processors execute the same workload.…”

Section: Multicore and Heterogeneous Computing At The Architecturallevelmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Rethinagiri

Palomar

Sobe

et al. 2015

Microprocessors and Microsystems

Self Cite

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a b s t r a c tDramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On the one hand, designers use technology scaling as one of the methods to face the phenomenon called dark silicon (only segments of a chip function concurrently due to power restrictions). On the other hand, designers use extreme-scale systems such as teradevices to meet the performance needs of their applications which in turn increases the power consumption of the platform. In order to overcome these challenges, we need novel computing paradigms that address energy efficiency. One of the promising solutions is to incorporate parallel distributed methodologies at different abstraction levels.The FP7 project ParaDIME focuses on this objective to provide different distributed methodologies (software-hardware techniques) at different abstraction levels to attack the power-wall problem. In particular, the ParaDIME framework will utilize: circuit and architecture operation below safe voltage limits for drastic energy savings, specialized energy-aware computing accelerators, heterogeneous computing, energy-aware runtime, approximate computing and power-aware message passing. The major outcome of the project will be a noval processor architecture for a heterogeneous distributed system that utilizes future device characteristics, runtime and programming model for drastic energy savings of data centers. Wherever possible, ParaDIME will adopt multidisciplinary techniques, such as hardware support for message passing, runtime energy optimization utilizing new hardware energy performance counters, use of accelerators for error recovery from sub-safe voltage operation, and approximate computing through annotated code. Furthermore, we will establish and investigate the theoretical limits of energy savings at the device, circuit, architecture, runtime and programming model levels of the computing stack, as well as quantify the actual energy savings achieved by the ParaDIME approach for the complete computing stack with the real environment.

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“…PETS was initially developed for the evaluation of MPSoC systems [10], [9], [11]. In ParaDIME, we have extended it to model a variety of other systems, including DSPs, FPGAs and multi-core (dual-and quad-core) ARM processors [13], [12], [15].…”

Section: ) Heterogeneous Computingmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy

Rethinagiri

Palomar

Sobe

et al. 2014

2014 17th Euromicro Conference on Digital System Design

Self Cite

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DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level

Cited by 6 publications

References 11 publications

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy

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