2014 Recent Advances in Engineering and Computational Sciences (RAECS) 2014
DOI: 10.1109/raecs.2014.6799523
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Designs of All Digital Phase Locked Loop

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Cited by 16 publications
(4 citation statements)
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“…At this point, the signal output from the demodulation In Figure 5 s block diagram, the FPGA generates a 100 kHz demodulation switch signal. This signal is then processed by the demodulation circuit to yield the output signal, as depicted in Equation (14). Subsequently, the signal is captured by AD and further processed within the FPGA.…”
Section: Phase Alignment System Designmentioning
confidence: 99%
See 1 more Smart Citation
“…At this point, the signal output from the demodulation In Figure 5 s block diagram, the FPGA generates a 100 kHz demodulation switch signal. This signal is then processed by the demodulation circuit to yield the output signal, as depicted in Equation (14). Subsequently, the signal is captured by AD and further processed within the FPGA.…”
Section: Phase Alignment System Designmentioning
confidence: 99%
“…This structure can achieve a reduction in 1/ f noise, thereby enhancing the performance of capacitive sensors. The other type is a digital structure [14], commonly implemented using DSP or FPFA [15], which can significantly enhance the processing speed and accuracy of the system. This aids in extracting information from weak modulated signals [16].…”
Section: Introductionmentioning
confidence: 99%
“…A PLL consists of a voltage controlled oscillator (VCO), phase detector and a low pass filter [7]. We implemented PLL digitally (digital phase locked loop) on the FPGA of NI GPIC using LabVIEW.…”
Section: A Implementation Of Pllmentioning
confidence: 99%
“…The PLL adjusts the control signal of the VCO by adding a phase frequency detector (PFD), which takes the integral of the phase difference between the feedback signal and the reference signal. Finally, the output frequency is locked when the phase difference is 0 [15]. Therefore, the PLL has stable performance.…”
Section: Introductionmentioning
confidence: 99%