Designing the power-handling capabilities of MOS power devices

Interface Trap Density near Midgap of SIPOS Films Deposited on Crystalline Silicon

“…Semi-insulating polycrystalline silicon films deposited pyrolytically by chemical vapor deposition at low pressure (LPCVD) are steadily finding a wider acceptance as an advantageous passivation for silicon high-voltage devices. The main effort of the investigations has been put on the bulk electrical properties of SIPOS films (1)(2)(3)(4)(5). Only a few data are available concerning the interface trap density in the upper half (energy E of the traps higher than E~ + 0.1 eV, Ei = intrinsic Fermi level) and the lower half of the bandgap (E lower than Ei -0.15 eV) (6,7).…”