Designing Custom Arithmetic Data Paths with FloPoCo

Dinechin, Florent de; Pasca, Bogdan

doi:10.1109/mdt.2011.44

Cited by 273 publications

(145 citation statements)

References 8 publications

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“…FixFIR, like most FloPoCo operators, was designed with a testbench generator [9]. All these operators reported here have been checked for last-bit accuracy by extensive simulation.…”

Section: Implementation and Resultsmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-Many digital filters and signal-processing transforms can be expressed as a sum of products with constants (SPC). This paper addresses the automatic construction of low-precision, but high accuracy SPC architectures: these architectures are specified as last-bit accurate with respect to a mathematical definition. In other words, they behave as if the computation was performed with infinite accuracy, then rounded only once to the low-precision output format. This eases the task of porting double-precision code (e.g. Matlab) to low-precision hardware or FPGA. The paper further discusses the construction of the most efficient architectures obeying such a specification, introducing several architectural improvements to this purpose. This approach is demonstrated in a generic, open-source architecture generator tool built upon the FloPoCo framework. It is evaluated on Finite Impulse Response filters for the ZigBee protocol.

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“…FixFIR, like most FloPoCo operators, was designed with a testbench generator [9]. All these operators reported here have been checked for last-bit accuracy by extensive simulation.…”

Section: Implementation and Resultsmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

Self Cite

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“…By comparison, the FPGA implementations see a much more gradual degradation of performance as the numerical accu- racy of operators is increased. This can be attributed to the specialized circuits produced by the Coregen [4] and FloPoCo [5] tools. Overall, the results suggest that for large dense matrices and for sufficiently large matrices, GPU platforms deliver greater throughput than competing FPGA platforms, but for smaller matrices, the combination of specialized operator structures and the absence of large kernel setup times makes FPGA implementation competitive.…”

Section: Resultsmentioning

confidence: 99%

“…This device is implemented in a 40nm process and our synthesis scripts targeted a 250MHz clock rate for each implementation. It was programmed using RTL design-entry incorporating floating-point cores from Xilinx Coregen [4] and FloPoCo [5].…”

Section: Equipmentmentioning

confidence: 99%

“…Xilinx LogiCORE IP [4] (Version 5.0) exploits the low-level architectural details of Xilinx FPGA fabric to provide high quality floating-point operators. For precision beyond 80 bits, arithmetic operators generated by FloPoCo [5] were used. FloPoCo does not offer as wide a range of options as Xilinx IP cores for trading-off latency and resource usage but allows us to generate cores with a wider range of precisions.…”

Section: Fpga Implementationmentioning

confidence: 99%

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GPU vs FPGA: A Comparative Analysis for Non-standard Precision

Minhas

Bayliss

Constantinides

2014

Lecture Notes in Computer Science

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Abstract. FPGAs and GPUs are increasingly used in a range of high performance computing applications. When implementing numerical algorithms on either platform, we can choose to represent operands with different levels of accuracy. A trade-off exists between the numerical accuracy of arithmetic operators and the resources needed to implement them. Where algorithmic requirements for numerical stability are captured in a design description, this trade-off can be exploited to optimize performance by using high-accuracy operators only where they are most required. Support for half and double-double floating point representations allows additional flexibility to achieve this. The aim of this work is to study the language and hardware support, and the achievable peak performance for non-standard precisions on a GPU and an FPGA. A compute intensive program, matrix-matrix multiply, is selected as a benchmark and implemented for various different matrix sizes. The results show that for large-enough matrices, GPUs out-perform FPGAbased implementations but for some smaller matrix sizes, specialized FPGA floating-point operators for half and double-double precision can deliver higher throughput than implementation on a GPU.

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“…Interestingly, recent research in the area of arithmetic generation has produced minimax approximations automatically using the Remez algorithm [34]. Again, these implementations are complex and designed for Field Programmable Gate Arrays (FPGAs) as denoted on the FloPoCo website [34]. This paper utilizes Chebyshev series approximations, because they provide a simple table-driven method for faithfully-rounded approximation to common elementary functions.…”

Section: Polynomial Function Approximationmentioning

confidence: 99%

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers and cubers. Initial coefficient values are obtained using a Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized coefficient values to meet a user-specified error constraint. The algorithm minimizes coefficient lengths to reduce lookup table requirements, maximizes the number of truncated columns to reduce the area, delay and power of the arithmetic units, and minimizes the maximum absolute error of the interpolator output. The method can be used to design interpolators to approximate any function to a user-specified accuracy, up to and beyond 53-bits of precision (e.g., IEEE double precision significand). Linear, quadratic and cubic interpolator designs that approximate reciprocal, square root, reciprocal square root and sine are presented and analyzed. Area, delay and power estimates are given for 16, 24 and 32-bit interpolators that compute the reciprocal function, targeting a 65 nm CMOS technology from IBM. Results indicate the proposed method uses smaller arithmetic units and has reduced lookup table sizes compared to previously proposed methods. The method can be used to optimize coefficients in other systems while accounting for coefficient quantization as well as truncation and rounding effects of multiple arithmetic units.

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Designing Custom Arithmetic Data Paths with FloPoCo

Cited by 273 publications

References 8 publications

Sum-of-product architectures computing just right

Sum-of-product architectures computing just right

GPU vs FPGA: A Comparative Analysis for Non-standard Precision

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

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