Designing and Verifying Communication Protocols Using Model Driven Architecture and Spin Model Checker

Kaliappan, Prabhu Shankar; Koenig, Hartmut; Kaliappan, Vishnu Kumar

doi:10.1109/csse.2008.976

Cited by 12 publications

(6 citation statements)

References 3 publications

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“…Kaliappan et al . stated that model‐driven design and development can be used to develop communication protocols. They also examined how UML state diagrams can be translated into Promela and can be checked with Spin model checker.…”

Section: Related Workmentioning

confidence: 99%

Model driven security framework for software design and verification

Deveci

Caglayan

2015

Security Comm Networks

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Information system security is receiving increasing attention every day because a security problem can cause serious financial loss or even loss of lives. Some of these security problems occur as a result of poor design practices, where important security functionality is not designed properly and is directly implemented later in the development cycle in an unmethodical way. Researchers have put a great deal of effort into defining processes and tools to design and develop more secure information systems. However, verification of the designed and developed security functionality is of utmost importance. In some cases, designs and codes also need to be formally or semi‐formally verified and certified by authorities. The Common Criteria is one of the widely used universal frameworks for evaluating the security functionality of information systems. In this paper, we propose a new framework, model driven security framework, for the analysis, design, and evaluation of security properties of information systems. Our aim is to support information system developers and evaluation authorities who implement the higher‐level Common Criteria (levels 6 and 7) security assurance process using formal methods based on Unified Modelling Language, Object Constraint Language, Promela, and Spin. Copyright © 2015 John Wiley & Sons, Ltd.

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Section: Related Workmentioning

confidence: 99%

Model driven security framework for software design and verification

Deveci

Caglayan

2015

Security Comm Networks

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“…The approach is restricted on a subset of SysML activity diagram constructs with control flow (data flow is missing). Kaliappan et al [13] propose a verification approach for system work-flow especially in communication protocol. The approach takes as input three UML diagrams: state machine diagram, activity diagram and sequence diagram.…”

Section: Related Workmentioning

confidence: 99%

A probabilistic and timed verification approach of SysML state machine diagram

Baouya

Bennouar

Mohamed

et al. 2015

2015 12th International Symposium on Programming and Systems (ISPS)

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Abstract-Timed-constrained and probabilistic verification approaches gain a great importance in system behavior validation. They enable the evaluation of system behavior according to the design requirements and ensure their correctness before any implementation. In this paper, we propose a probabilistic and timed verification framework of State Machine diagrams extended with time and probability features. The approach consists on mapping the extended State Machine diagram to its equivalent probabilistic timed automata that is expressed in PRISM language. To check the functional correctness of the system under test, the properties are expressed in PCTL temporal logic. We demonstrate the approach efficiency by analyzing performability properties on a Automatic Teller Machine (ATM) case study.

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“…Timing verification is not considered. Kaliappan et al [12] propose a verification approach for system workflow especially in communication protocol. The approach takes as input three UML diagrams: state machine diagram, activity diagram and sequence diagram.…”

Section: Related Workmentioning

confidence: 99%

On the Probabilistic Verification of Time Constrained SysML State Machines

Baouya¹,

Bennouar²,

Mohamed³

et al. 2015

Communications in Computer and Information Science

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Abstract. Software and hardware design of complex systems is becoming difficult to maintain and more time and effort are spent on verification than on construction. One of the reason is the number of constraints that must be hold by the system. Recently, Formal methods such as probabilistic approaches gain a great importance in real-time systems verification including avionic systems and industrial process controllers. In this paper, we propose a probabilistic verification framework of SysML state machine diagrams extended with time and probability features. The approach consists of mapping a SysML state machine diagrams to PRISM input language. To ensure the correctness of proposed approach, we capture the semantics of both SysML state machine diagrams and their generated PRISM code. We demonstrate the approach efficiency by analyzing PCTL temporal logic on ATM case study.

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Designing and Verifying Communication Protocols Using Model Driven Architecture and Spin Model Checker

Cited by 12 publications

References 3 publications

Model driven security framework for software design and verification

Model driven security framework for software design and verification

A probabilistic and timed verification approach of SysML state machine diagram

On the Probabilistic Verification of Time Constrained SysML State Machines

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