Designing an FPGA-Accelerated Homomorphic Encryption Co-Processor

Cousins, David Bruce; Rohloff, Kurt; Sumorok, Daniel

doi:10.1109/tetc.2016.2619669

Cited by 48 publications

(35 citation statements)

References 21 publications

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“…In this paper we design our domain specific processor architecture to support applications with small multiplicative depth, say up to 4. This multiplicative depth is enough to support several statistical applications such as privacy-friendly forecasting for the smart grid [4], evaluation of low-complexity block cipher such as Rasta [25] on ciphertext, private information retrieval or encrypted search in a table of 2 16 entries, encrypted sorting etc. To achieve a multiplicative depth of four and at least 80-bit security [26], we set the size of modulus q to 180-bit, the length of polynomials to 4096 coefficients, the standard deviation of the error distribution to 102 and the width of the larger modulus Q to at least 372-bit.…”

Section: Parameter Setmentioning

confidence: 99%

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FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

Roy

Turan

Järvinen

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multicore multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGAclock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.

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Section: Parameter Setmentioning

confidence: 99%

“…In the literature there are several reported hardware implementation that try to speedup performance of HE schemes [11,12,13,14,15,16,17,18,19,20,21]. Several of these reported implementations report only simulation based results.…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

Roy

Turan

Järvinen

et al. 2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

show abstract

“…In 2016, the FPGA-based computing accelerator was used as part of a co-processor homomorphic encryption processing unit to execute important computing applications [19]. Advanced design and computation accelerators based on FPGA are introduced in this study as part of a co-processor homomorphic encryption processing unit.…”

Section: Related Workmentioning

confidence: 99%

Hardware Implementation of an Encryption for Enhancement DGHV

Mahmood¹,

Ibrahem²

2019

Iraqi Journal of ICT

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

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“…A non-uniform distribution, which forms no plausible meaning signifies an incorrect plaintext and key. Moreover, the advent of high-processing tools such as FPGA, GPU also makes the brute-force attack to be highly successful [14], [15], [16]. Therefore, an attacker that intercepts an encrypted message has a high chance of recovering the key and subsequently the message encrypted under such key by using the distinguisher techniquewhich is to judge the decryption output based on the distribution/structure of the message.…”

Section: Introductionmentioning

confidence: 99%

Modified honey encryption scheme for encoding natural language message

Omolara¹,

Jantan²

2019

IJECE

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Conventional encryption schemes are susceptible to brute-force attacks. This is because bytes encode utf8 (or ASCII) characters. Consequently, an adversary that intercepts a ciphertext and tries to decrypt the message by brute-forcing with an incorrect key can filter out some of the combinations of the decrypted message by observing that some of the sequences are a combination of characters which are distributed non-uniformly and form no plausible meaning. Honey encryption (HE) scheme was proposed to curtail this vulnerability of conventional encryption by producing ciphertexts yielding valid-looking, uniformly distributed but fake plaintexts upon decryption with incorrect keys. However, the scheme works for only passwords and PINS. Its adaptation to support encoding natural language messages (e-mails, human-generated documents) has remained an open problem. Existing proposals to extend the scheme to support encoding natural language messages reveals fragments of the plaintext in the ciphertext, hence, its susceptibility to chosen ciphertext attacks (CCA). In this paper, we modify the HE schemes to support the encoding of natural language messages using Natural Language Processing techniques. Our main contribution was creating a structure that allowed a message to be encoded entirely in binary. As a result of this strategy, most binary string produces syntactically correct messages which will be generated to deceive an attacker who attempts to decrypt a ciphertext using incorrect keys. We evaluate the security of our proposed scheme.

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Designing an FPGA-Accelerated Homomorphic Encryption Co-Processor

Cited by 48 publications

References 21 publications

FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

Hardware Implementation of an Encryption for Enhancement DGHV

Modified honey encryption scheme for encoding natural language message

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