Designing Algorithms for the EMU Migrating-threads-based Architecture

Belviranlı, Mehmet E.; Lee, Seyong; Vetter, Jeffrey S.

doi:10.1109/hpec.2018.8547571

Cited by 8 publications

(4 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other recent work has also looked to extend from low-level characterizations like those presented here by providing initial Emu-focused implementations of Breadth-First Search [11], Jaccard index computation [42], bitonic sort, [66] and compiler optimizations like loop fusion, edge flipping, and remote updates to reduce migrations [16].…”

Section: Related Workmentioning

confidence: 99%

“…Previous work has investigated the initial Emu architecture design [23], algorithmic designs for merge and radix sorts on the Emu hardware [51], and baseline performance characteristics of the Emu Chick hardware [11,36]. This investigation is focused on determining how irregular algorithms perform on the prototype Chick hardware and how we implement specific algorithms so that they can scale to a rack-scale Emu and beyond.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Programming Strategies for Irregular Algorithms on the Emu Chick

Hein¹,

Eswar²,

Yaşar³

et al. 2019

Preprint

View full text Add to dashboard Cite

The Emu Chick prototype implements migratory memory-side processing in a novel hardware system. Rather than transferring large amounts of data across the system interconnect, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each remote memory read. Previous work has characterized the performance of the Chick prototype in terms of memory bandwidth and programming differences from more typical, non-migratory platforms, but there has not yet been an analysis of algorithms on this system. This work evaluates irregular algorithms that could benefit from the lightweight, memory-side processing of the Chick and demonstrates techniques and optimization strategies for achieving performance in sparse matrix-vector multiply operation (SpMV), breadth-first search (BFS), and graph alignment across up to eight distributed nodes encompassing 64 nodelets in the Chick system. We also define and justify relative metrics to compare prototype FPGA-based hardware with established ASIC architectures. The Chick currently supports up to 68x scaling for graph alignment, 80 MTEPS for BFS on balanced graphs, and 50% of measured STREAM bandwidth for SpMV.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Programming Strategies for Irregular Algorithms on the Emu Chick

Hein¹,

Eswar²,

Yaşar³

et al. 2019

Preprint

View full text Add to dashboard Cite

show abstract

“…Simulations of architectures focusing on near-data processing [14] including in-memory [15] and near-memory [16] show great promise for increasing performance while also drastically reducing energy usage. Other than our previous study [1], and related work on characterizing the Emu by other research groups [17,18] few of these architectures have been implemented in hardware, even FPGAs, limiting the data scales on which applications can be evaluated.…”

Section: Related Workmentioning

confidence: 99%

“…Other recent work has also looked to extend from low-level characterizations like those presented here by providing initial Emu-focused implementations of Breadth-First Search [17], Jaccard index computation [27], bitonic sort, [28] and compiler optimizations like loop fusion, edge flipping, and remote updates to reduce migrations [29].…”

Section: Related Workmentioning

confidence: 99%

A microbenchmark characterization of the Emu chick

Young

Hein²,

Eswar

et al. 2019

Parallel Computing

View full text Add to dashboard Cite

The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less "Gossamer" cores for computational work and rely on a typical stationary core (PowerPC) to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation [1] of the the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. We compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results demonstrate that for many basic operations the Emu Chick can use available memory bandwidth more efficiently than a more traditional, cache-based architecture although bandwidth usage suffers for computationally intensive workloads like SpMV. Moreover, the Emu Chick provides stable, predictable performance with up to 65% of the peak bandwidth utilization on a random-access pointer chasing benchmark with weak locality.

show abstract