Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

Lunteren, Jan van; Hagleitner, Christoph; Heil, Timothy; Biran, Giora; Shvadron, U.; Atasu, Kubilay

doi:10.1109/micro.2012.49

Cited by 52 publications

(28 citation statements)

References 27 publications

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“…Therefore, researchers are putting their efforts to improve the DFA based matching engines by focusing on reducing the memory footprint as it is the major drawback of DFAs; whereas less work is being done to speed up the look-up process in DFA based matching engines. Some hardware based approaches, reported in Lunteren et al (2012), Brodie et al (2006) and , have been proposed for pattern matching which either make use of field-programmable gate arrays (FPGA) or application-specific integrated circuits (ASIC) to achieve high throughputs in DFA based matching engines. However, they do not provide the type of flexibility which the software based approaches can provide when it comes to update the regular expressions.…”

Section: Q3mentioning

confidence: 99%

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Speculative parallel pattern matching using stride-k DFA for deep packet inspection

Najam

Younis

Rasool

2015

Journal of Network and Computer Applications

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Section: Q3mentioning

confidence: 99%

“…A number of FPGA and ASIC approaches have been proposed which can provide higher throughput due to the parallelism offered by the hardware (Lunteren et al, 2012;Brodie et al, 2006;. These higher throughputs are difficult to be achieved using software based techniques which make use of memory to store automaton.…”

Section: Related Workmentioning

confidence: 99%

Speculative parallel pattern matching using stride-k DFA for deep packet inspection

Najam

Younis

Rasool

2015

Journal of Network and Computer Applications

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“…Some works have presented solutions using FPGAs and ASICs for DFA based pattern matching, but not many of these hardware solutions have proven flexible [9][10] [11]. As mentioned earlier, it is getting extremely hard to detect malicious traffic, especially due to its changing trend in payload patterns.…”

Section: Related Workmentioning

confidence: 99%

Multi-byte Pattern Matching Using Stride-K DFA for High Speed Deep Packet Inspection

Najam

Younis

Rasool

2014

2014 IEEE 17th International Conference on Computational Science and Engineering

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Deep packet inspection (DPI) is one of the crucial tasks in modern intrusion detection and intrusion prevention systems. It allows the inspection of packet payload using patterns. Modern DPI based systems use regular expressions to define these patterns. Deterministic finite automata (DFA) is considered to be an ideal choice for performing regular expression matching due to its O(1) processing complexity. However, DFAs consume large memory to store its state transition table, but this problem gets worsened when stride level of the DFA is increased. Though, increasing stride level brings significant increase in the overall speedup of the matching engine but as a tradeoff it consumes large memory.In this paper, we present stride-k speculative parallel pattern matching (SPPM), a technique in which a packet is first split up into two chunks and then multiple bytes per chunk are inspected at a time using stride-k DFA. Furthermore, we present a stride-k DFA compression technique using alphabet compression table (ACT) to reduce the memory requirements of stride-k DFA. We have implemented the single threaded algorithm for stride-2 SPPM. Results show that the use of stride-2 SPPM can overall increase the pattern matching speed by up to 30% as compared to traditional DFA matching, and a significant reduction of over 70% in the number of iterations required for packet processing. Secondly, over 65% reduction in the number of transitions has been achieved using ACT for stride-2 DFA implementation.

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“…For traditional computers, finite automata processing is challenging because it requires unpredictable memory references and control transfers that reduce the effectiveness of branch prediction and instruction level parallelism -staples of high performance CPUs [39] and GPUs [40][41][42]. As a result, high performance FA applications have historically resorted to custom hardware approaches (ASICs [43,44] and FPGAs [45][46][47]) to meet demanding real-time requirements.…”

Section: Introductionmentioning

confidence: 99%

Fast support for unstructured data processing

You

Hoang

Becchi

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

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We propose the Unified Automata Processor (UAP), a new architecture that provides general and efficient support for finite automata (FA). The UAP supports a wide range of existing finite automata models (DFAs, NFAs, A-DFAs, JFAs, counting-DFAs, and countingNFAs), and future novel FA models. Evaluation on realistic workloads shows that UAP implements all models efficiently, achieving line rates 94.5% of ideal. A single UAP lane delivers line rates 50x greater than software approaches on CPUs and GPUs. Scaling UAP to 64 lanes achieves FA transition throughputs as high as 295 Gbps, more than 100x higher than CPUs and GPUs, and even exceeding ASIC approaches such as IBM's RegX by 6x. With efficient support for multiple input streams, UAP achieves throughputs that saturate even high speed stacked DRAM memory systems.The UAP design and implementation is efficient in instructions executed, memory references, and energy. UAP achieves a 1.2 Ghz clock rate (32nm TSMC CMOS), and a 64-lane UAP requires only 2.2 mm 2 and 563 mW. At these levels of performance and energy-efficiency, UAP is a promising candidate for integration into generalpurpose computing architectures.

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Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

Cited by 52 publications

References 27 publications

Speculative parallel pattern matching using stride-k DFA for deep packet inspection

Speculative parallel pattern matching using stride-k DFA for deep packet inspection

Multi-byte Pattern Matching Using Stride-K DFA for High Speed Deep Packet Inspection

Fast support for unstructured data processing

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