Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers

Song, Yongwoon; Choi, Dongkeon; Lee, Hyukjun

doi:10.1587/transele.2019ecs6003

Cited by 1 publication

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To design scalable high bandwidth packet buffer for routers/switches, various DRAM based memory architectures with SRAM buffers have been proposed [7] [8] [9] [10] [22]. All these works basically differ in how to design SRAM input/output buffers in the memory controller to support the DRAM-based memory (packet buffer).…”

Section: A Packet Processor and Packet Buffermentioning

confidence: 99%

See 1 more Smart Citation

High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM

Song,

Lee,

Lee

2023

IEEE Access

Self Cite

View full text Add to dashboard Cite

Significant challenges are posed in the design of routers and switches by the explosive growth of internet traffic and the stringent requirements for high availability in the research area of computer networks. Ensuring both high performance and system availability is crucial. To achieve this, recent advancements have turned to the utilization of non-volatile memories, such as magnetic RAM (MRAM) and phase-change memory (PCM), in routing lookup tables and packet buffers of routers and switches. However, the use of non-volatile memories show limitations in scaling with respect to bandwidth and capacity. With the increasing clock speed of the IO bus, high-capacity memories like PCM exhibit limited scalability in performance since accessing the cells in the array does not show significant improvement. Meanwhile, attempts to enhance the capacity of low-access-latency non-volatile memories like spin-transfer torque MRAM (STT-MRAM) through smaller cell sizes result in an adverse impact on the write time. The goal of this study is to design a packet buffer that can provide high bandwidth and ensure high availability. To achieve this, a multi-retention time MRAM-based packet buffer is presented, along with a packet mapping method, which aims to overcome the scalability challenge while ensuring high availability. The two-tier packet buffer (TT-PB) structure implements a small/fast MRAM combined with a large/slow MRAM, which outperforms the baseline MRAM/PCM hybrid memory-based packet buffer by up to 16% and 58% for 1.6 and 3.2 GHz IO bus clocks. For input, internet-mix packet traffic is utilized to depict realistic internet traffic. Moreover, the proposed latency-aware multi-retention time MRAM-based packet buffer structure (MR-PB) consists of short and long retention time MRAM partitions. It identifies the buffering latency demands of various packets and writes the packets into partitions that have sufficient retention time to accommodate the required buffering latencies, thereby achieving an optimal write latency for each packet. With this scheme, an additional speedup of up to 5.27% is achieved over TT-PB.INDEX TERMS IP router, packet buffer, spin-transfer torque magnetic RAM (STT-MRAM), multiretention time

show abstract

Section: A Packet Processor and Packet Buffermentioning

confidence: 99%

“…To address this issue, a method using SRAM and DRAM as parallel memories in the packet buffer is proposed [22]. In the method, packets degrading row buffer locality are mapped to the SRAM portion to enhance the scalability.…”

Section: A Packet Processor and Packet Buffermentioning

confidence: 99%