Designing a clock cycle accurate application with high-level synthesis

Lahti, Sakari; Vanne, Jarno; Hämäläinen, Timo D.

doi:10.1109/iecon.2016.7793783

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…When facing these differences, sometimes it is possible to still attain the same bit-level and cycle-level behavior by emulating the desired but unavailable primitive with an available one. 10 This emulation will add an overhead cost in logic resources and logic delay.…”

Section: Limitationsmentioning

confidence: 99%

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Using Vivado-HLS for Structural Design

Zhao

Hoe

2017

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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There have been ample successful examples of applying Xilinx Vivado's "function-to-module" high-level synthesis (HLS) where the subject is algorithmic in nature. In this work, we carried out a design study to assess the effectiveness of applying Vivado-HLS in structural design. We employed Vivado-HLS to synthesize C functions corresponding to standalone network-on-chip (NoC) routers as well as complete multi-endpoint NoCs. Interestingly, we find that describing a complete NoC comprising router submodules faces fundamental difficulties not present in describing the routers as standalone modules. Ultimately, we succeeded in using Vivado-HLS to produce router and NoC modules that are exact cycle-and bit-accurate replacements of our reference RTL-based router and NoC modules. Furthermore, the routers and NoCs resulting from HLS and RTL are comparable in resource utilization and critical path delay. Our experience subjectively suggests that HLS is able to simplify the design effort even though much of the structural details had to be provided in the HLS description through a combination of coding discipline and explicit pragmas. The C++ source code can be found at

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Section: Limitationsmentioning

confidence: 99%

“…In prior work, Kapre and Gray have used Vivado-HLS to generate standalone router module for Hoplite, a lightweight FPGA overlay NoC [8]. Lahti, et al showed how to develop a cycle-accurate structural module of a I2C bus controller using Catapult C [10].…”

Section: High-level Synthesismentioning

confidence: 99%

Using Vivado-HLS for Structural Design

Zhao

Hoe

2017

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications

Sjövall

Lemmetti

Vanne

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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High Efficiency Video Coding (HEVC) is the key enabling technology for numerous modern media applications. Overcoming its computational complexity and customizing its rich features for real-time HEVC encoder implementations, calls for automated design methodologies. This article introduces the first complete High-Level Synthesis (HLS) implementation for HEVC intra encoder on FPGA. The C source code of our open-source Kvazaar HEVC encoder is used as a design entry point for HLS that is applied throughout the whole encoder design process, from data-intensive coding tools like intra prediction and discrete transforms to more control-oriented tools such as context-adaptive binary arithmetic coding (CABAC). Our prototype is run on Nokia AirFrame Cloud Server equipped with 2.4 GHz dual 14-core Intel Xeon processors and two Intel Arria 10 PCIe FPGA accelerator cards with 40 Gigabit Ethernet. This proof-of-concept system is designed for hardware-accelerated HEVC encoding and it achieves real-time 4K coding speed up to 120 fps. The coding performance can be easily scaled up by adding practically any number of network-connected FPGA cards to the system. These results indicate that our HLS proposal not only boosts development time, but also provides previously unseen design scalability with competitive performance over the existing FPGA and ASIC encoder implementations.

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Designing a clock cycle accurate application with high-level synthesis

Cited by 2 publications

References 16 publications

Using Vivado-HLS for Structural Design

Using Vivado-HLS for Structural Design

High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications

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