Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors

Nikiema, Pegdwende Romaric; Kritikakou, Angeliki; Traiola, Marcello; Sentieys, Olivier

doi:10.1109/dsn-s58398.2023.00062

Cited by 4 publications

(1 citation statement)

References 15 publications

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“…Sometimes, the bus protection is reduced only to providing data EDAC checksum, or the protection is completely omitted. For example, it is assumed in [50] that the EDAC mechanism protects instruction and data memory, whereas the core in [18] provides only a checksum for data. Study [51] implements a soft-core processor into a field-programmable gate array (FPGA) while connecting a dedicated EDAC module between the core and memory, providing data encoding/decoding.…”

Section: Existing Protection Approachesmentioning

confidence: 99%

On-Chip Bus Protection against Soft Errors

Mach,

Kohútka,

Čičák

2023

Electronics

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The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties that provide higher performance also lead to higher susceptibility to transient faults caused by radiation. Many approaches exist for protecting individual processor cores, but the protection of interconnect buses is studied less. This paper describes the importance of protecting on-chip bus interconnects and reviews existing protection approaches used in processors for mission and safety-critical processors. The protection approaches are sorted into three groups: information, temporal, and spatial redundancy. Because the final selection of the protection approach depends on the use case and performance, power, and area demands, the three groups are compared according to their fundamental properties. For better context, the review also contains information about existing solutions for protecting the internal logic of the cores and external memories. This review should serve as an entry point to the domain of protecting the on-chip bus interconnect and interface of the core.

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Section: Existing Protection Approachesmentioning

confidence: 99%