Design tradeoffs for the alpha EV8 conditional branch predictor

Seznec, André; Felix, Stephen; Krishnan, V.; Sazeides, Yiannakis

doi:10.1109/isca.2002.1003587

Cited by 103 publications

(116 citation statements)

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“…With folded modulo-path history, we use f addresses hashed together. Folded modulo-path history can be considered the path-history analogue of the folded long branch outcome histories used in other predictors such as 2bc-gskew [14]. Figure 3 shows an example PBNP with P = 4 and f = 3 for a total path length of 12 while only using four tables.…”

Section: Folded Modulo-path Historymentioning

confidence: 99%

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors

Loh

Jiménez

2008

Int J Parallel Prog

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Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challenging to implement in future high-performance processors. In particular, the path-based neural predictor (PBNP) and the piecewise-linear (PWL) predictor require deep pipelining and additional area to support checkpointing for misprediction recovery. The complexity of the PBNP predictor stems from the fact that the path history length, which determines the number of tables and pipeline stages, is equal to the history length, which is typically very long for high accuracy. We propose to decouple the path-history length from the outcome-history length through a new technique called modulo-path history. By allowing a shorter path history, we can implement the PBNP and PWL predictors with significantly fewer tables and pipeline stages while still exploiting a traditional long branch outcome history.

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Section: Folded Modulo-path Historymentioning

confidence: 99%

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors

Loh

Jiménez

2008

Int J Parallel Prog

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“…Since larger branch predictors are more accurate, modern microarchitectures attempt to overcome the access delay problem by using complex schemes such as hierarchical overriding branch predictors, in which a simple and quick predictor is backed up by a large, complex, and slower predictor [7]. This tech- nique was used for the Alpha EV6 branch predictor [9] and was built into the design for the Alpha EV8 branch predictor [14]. Because of penalties associated with their implementations, the extra accuracy provided by such complex predictors does not yield a proportionate increase in performance.…”

Section: Better Accuracy Doesn't Always Mean Better Performancementioning

confidence: 99%

“…Seznec et al describe the Compaq EV8 hybrid predictor, which has four components: two two-level predictors, one bi-modal predictor, and one metapredictor [14]. The hardware budget for this predictor is 352 Kbits.…”

Section: Some Implemented Branch Predictorsmentioning

confidence: 99%

“…In addition to table accesses, these predictors incur extra delay by, for instance, combining information from multiple tables, using an index read from one table to access another table, computing information such as the majority of two counters [14], or even computing the dot product of a two vectors [8].…”

Section: Increased Predictor Complexitymentioning

confidence: 99%

“…This trend will continue into the future, with branch predictor hardware budgets running into the scores or hundreds of kilobytes. For example, the design for the Compaq EV8 included a hybrid branch predictor with approximately 45KB of state [14]. Figure 1 shows the arithmetic mean misprediction rates achieved over the SPEC 2000 integer benchmarks by extending several branch predictors from the literature into large hardware budgets, as well two very complex but highly accurate predictors: the multi-component hybrid predictor [5] and the perceptron predictor [8].…”

Section: Introductionmentioning

confidence: 99%

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Reconsidering complex branch predictors

Jiménez

The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.

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To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their designs, taking advantage of the increasing numbers of transistors available on a chip. Unfortunately, because of penalties associated with their implementations, the extra accuracy provided by many branch predictors does not produce a proportionate increase in performance. Specifically, we show that the techniques used to hide the latency of a large and complex branch predictor do not scale well and will be unable to sustain IPC for deeper pipelines.We investigate a different way to build large branch predictors. We propose an alternative predictor design that completely hides predictor latency so that accuracy and hardware budget are the only factors that affect the efficiency of the predictor. Our simple design allows the predictor to be pipelined efficiently by avoiding difficulties introduced by complex predictors. Because this predictor eliminates the penalties associated with complex predictors, overall performance exceeds that of even the most accurate known branch predictors in the literature at large hardware budgets. We conclude that as chip densities increase in the next several years, the accuracy of complex branch predictors must be weighed against the performance benefits of simple branch predictors.

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A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

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Design tradeoffs for the alpha EV8 conditional branch predictor

Cited by 103 publications

References 14 publications

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors

Reconsidering complex branch predictors

A survey of techniques for dynamic branch prediction

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