2017
DOI: 10.1117/1.jmm.16.1.013502
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Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

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Cited by 9 publications
(2 citation statements)
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“…The integration of BCP-based nanopatterning into FinFET fabrication requires the co-optimization of the process, design, and layout. Some simulation work has been carried out to find optimal designs for the guide pattern mask, fin, and via structures [111,112]. To date, DSA has demonstrated good capabilities in dense line/space patterning.…”
Section: Finfet Fabricationmentioning
confidence: 99%
“…The integration of BCP-based nanopatterning into FinFET fabrication requires the co-optimization of the process, design, and layout. Some simulation work has been carried out to find optimal designs for the guide pattern mask, fin, and via structures [111,112]. To date, DSA has demonstrated good capabilities in dense line/space patterning.…”
Section: Finfet Fabricationmentioning
confidence: 99%
“…The downscaling of pattern dimensions in microelectronics has long passed the limits of 193 nm immersion lithography. Design-technology co-optimization (DTCO) allowed manufacturers to keep the pace in pitch scaling for the past decade, waiting for extreme-UV (EUV) lithography to become high-volume production-ready. The steady progress brought the pitches of the densest structures in the current most advanced CMOS nodes down to around 30 nm.…”
Section: Introductionmentioning
confidence: 99%