Design strategy and simulation of single-gate SET for novel SETMOS hybridization

Novel Hybrid SETMOS Logic for Ultra-low-power Applications

“…1a shows the SG-SET structure with its critical dimensions simulated in TCAD [21]. The tunnel barrier optimization and island engineering techniques have been carried out to obtain the best dimensions and materials for tunnel junctions and island of SG-SET [19,21,26]. The roomtemperature output characteristic is plotted and then calibrated with fabricated devices, as shown in Fig.…”

“…2a shows the symbol and RC model of SG-SET. The SG-SET parameters are evaluated based on the criteria of room temperature operation, and CMOS bias compatibility [21]. The gate capacitance calculated from CMOS bias (e/2V DD ) is 0.1 aF.…”

“…The gate capacitance calculated from CMOS bias (e/2V DD ) is 0.1 aF. The tunnel junction capacitance is calculated from the parallel plate model as 0.0468 aF [21] from TCAD simulations. This gives total capacitance (C Σ =C G +2C J ) of 0.193 aF [21].…”

“…The CMOS compatibility and silicon processes are also advantages [20]. This hybridization method gives ultra-low-power consumptions than CMOS and lesser propagation delay than other SETMOS hybridization techniques [20,21]. Also, using this kind of hybridization, co-tunneling can be avoided compared to SET-only based circuits [6].…”

“…Also, using this kind of hybridization, co-tunneling can be avoided compared to SET-only based circuits [6]. Our earlier work also comprises the device planning and optimization of SG-SET using TCAD simulation, observing CB and QMT at room temperature, and mathematical modeling to express the drain current using Gibbs free energy [21,22]. The tunnel resistance, R T is also extracted as 20 MΩ .…”