Design Space Exploration of the European Option Benchmark using Hyperstreams

ACM Trans. Reconfigurable Technol. Syst.

et al. 2009

This article explores the application of reconfigurable hardware to the acceleration of financial computation using tree-based pricing models. Two parallel pipelined architectures have been developed for option valuation using binomial trees and trinomial trees, with support for concurrent evaluation of independent options to achieve high pricing throughput. Our results show that the tree-based models executing on a Virtex 4 field programmable gate array (FPGA) at 82.7 MHz with fixed-point arithmetic can run over 160 times faster than a Core2 Duo processor at 2.2 GHz. The FPGA implementation is two times faster than the nVidia Geforce 7900GTX processor with 24 pipelines at 650 MHz, and 27%-35% slower than the nVidia Geforce 8600GTS processor with 32 Pipelines at 1450 MHz. Our preliminary experiments also indicate that while an FPGA implementation can be slower than a GPU, it could be more efficient when power consumption is taken into account.

Section: Resultsmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models

Jin

Thomas

ACM Trans. Reconfigurable Technol. Syst.

et al. 2009

“…We can see that our proposed approach allocates DSP blocks between loop parallelization and pipelining to achieve better balanced and faster designs. We have implemented the MCS of Asian Option Pricing using the HyperStream library [22] on the target platform. Because the library implementation tries to greedily pipeline all operations, we can only implement the application by first allocating the DSPs to pipeline the innermost loop, and thus the resources to parallelize the outer loop iterations are limited.…”

Section: Fast Motion Estimation Algorithm By Merritt Andmentioning

confidence: 99%

Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms

Liu

Todman

et al. 2010

J Sign Process Syst

The MapReduce pattern can be found in many important applications, and can be exploited to significantly improve system parallelism. Unlike previous work, in which designers explicitly specify how to exploit the pattern, we develop a compilation approach for mapping applications with the MapReduce pattern automatically onto Field-Programmable Gate Array (FPGA) based parallel computing platforms. We formulate the problem of mapping the MapReduce pattern to hardware as a geometric programming model; this model exploits loop-level parallelism and pipelining to give an optimal implementation on given hardware resources. The approach is capable of handling single and multiple nested MapReduce patterns. Furthermore, we explore important variations of MapReduce, such as using a linear structure rather than a tree structure for merging intermediate results generated in parallel. Results for six benchmarks show that our approach can find performance-optimal designs in the design space, improving system performance by up to 170 times compared to the initial designs on the target platform.

“…In recent years FPGAs have increasingly been used as a co-processor for high performance reconfigurable computing, where they are used to accelerate complicated numerical procedures such as finance applications. Although research has shown that FPGAs are suitable for accelerating many computationally intensive applications [1], there is limited actual deployment for high performance computing applications.…”

Section: Introductionmentioning

confidence: 99%

Automated application acceleration using software to hardware transformation

Jin

Thomas

2009 International Conference on Field-Programmable Technology

2009

Abstract-This paper describes an approach that allows applications to be developed in a software language, while taking advantage of hardware by facilities that automatically transform such software programs for hardware accelerators. A demonstration of this approach has been built for the C# language. Three case studies in numerical integration show that the automatically generated hardware accelerators can achieve similar speed-ups to manually optimised versions. In particular, the automatically generated accelerator running on an xc4vlx160 FPGA at 83MHz with single precision arithmetic can be more than 18 times faster and up to 143 times more power efficient than a Pentium 4 processor at 3.6GHz, while the double precision accelerator running at 64MHz is 7 times faster and 77 times more power efficient.