Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

Biswas, Prasenjit; Varadarajan, Keshavan; Alle, Mythri; Nandy, S. K.; Narayan, Ranjani

doi:10.1109/icsamos.2010.5642058

Cited by 6 publications

(6 citation statements)

References 12 publications

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“…6.27 and Fig.6. 28. Other kernels have very close values, due to small differences in switching activity, for the power.…”

Section: Time Energy and Scalabilitymentioning

confidence: 88%

Section: Cgrasmentioning

confidence: 99%

“…REDEFINE CGRA implementation of QR factorization is presented in [28] where the performance is achieved by Custom Functional Unit (CFU) inside Compute Elements (CEs). The focus of [28] is on emulation of systolic schedule for GR on REDEFINE and hence synthesis of systolic array on REDEFINE. Other optimizations on REDE-FINE CGRAs are also attempted in [111,112], firstly targeting algorithmic optimization which is then exploited for CGRA-based acceleration.…”

Section: Cgrasmentioning

confidence: 99%

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Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.

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“…6.27 and Fig.6. 28. Other kernels have very close values, due to small differences in switching activity, for the power.…”

Section: Time Energy and Scalabilitymentioning

confidence: 88%

Section: Cgrasmentioning

confidence: 99%

Section: Cgrasmentioning

confidence: 99%

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Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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“…REDEFINE CGRA implementation of Q-R decomposition is presented in [13] where the performance is achieved by Custom Functional Unit (CFU) inside Compute Elements (CEs). The focus of [13] is on emulation of systolic schedule for GR on REDEFINE and hence synthesis of systolic array on REDEFINE.…”

Section: Previous Implementationsmentioning

confidence: 99%

“…The focus of [13] is on emulation of systolic schedule for GR on REDEFINE and hence synthesis of systolic array on REDEFINE. The major disadvantage of [13] is the high computational complexity, coupled with high latency problems on REDEFINE's NoC, as matrix size increases.…”

Section: Previous Implementationsmentioning

confidence: 99%

Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation

Rakossy

Merchant

Acosta-Aponte

et al. 2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth. Using two flavors of Column-wise Givens rotation, derived from traditional Fast Givens and Square root and Division Free Givens Rotation algorithms the architecture is thoroughly evaluated for scalability, speed, area and energy. Combining an efficient mapping strategy of the highly parallel algorithms capable of annihilation of multiple elements of a column of the input matrix and using the new features of the architecture, 9 architectural variants were explored achieving a clean trade-off of execution speed versus area, while keeping relatively constant energy.

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