Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators

Abstract

This work proposes three different methods to automatically characterize heterogeneous MPSoCs com-posed of a variable number of masters (in the form of processors) and hardware accelerators (HWaccs). These hardware accelerators are given as Behavioral IPs (BIPs) mapped as loosely coupled accelerators on a shared bus system ( i.e. AHB, AXI). BIPs have a distinct advantage over traditional RT-level based IPs given VHDL or Verilog: The ability to generate micro-architectures with different area vs. perfor-mance trade-offs from the same description. This is usually done by specifying different synthesis direc-tives in the form of pragmas. This in turn implies that using different mixes of the accelerators' micro-architectures lead to SoCs with unique area vs. performance trade-offs. Two of the three methods proposed are based on cycle-accurate simulations of the complete MPSoC, while the third method accelerates this exploration by performing it on a Configurable SoC FPGA. Exten-sive experimental results compare these three methods and highlight their strengths and weaknesses. * Corresponding author.ten used as HWAccs on these heterogeneous MPSoCs. The International Technology Roadmap for Semiconductors (ITRS) already suggested in 2013 that by 2020 a 10x productivity increase for designing complex SoCs was needed [1] . Two main factors were predicted to help to achieve this goal. The first is the re-use of components. ITRS estimates that around 90% of the SoCs will be composed of re-used components. Secondly, the use of new design methodologies to raise the level of abstraction i.e . HLS. The use of HLS has led to a new market for 3PBIPs. One of the main advantages of BIPs is that they are much easier to re-use than traditional RT-level IPs. Moreover, micro-architectures of different area vs. performance trade-offs can be easily obtained by synthesizing the behavioral description with different synthesis options. This is typically done by setting different synthesis options in the form of pragmas (comments) inserted directly into the source code or through global synthesis options. For example, these options can control how to synthesize arrays (register or RAM), if a function should be inlined or not and if loops should be fully unrolled, partially unrolled, not unrolled or pipelined.FPGA vendors have also embraced this new paradigm and have released their own Programmable or Configurable SoCs (CSoCs), e.g . Altera's Cyclone V SoC and Xilinx's Zynq FPGA. These CSoCs contain multiple embedded cores mainly in the form of ARM Cortex A9 and reconfigurable fabric onto which to map the

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

“…Xu et al [123] propose a methodology for performing DSE using MPSoC devices. This work presents three methods to automatically carry out the exploration: two based on simulation (cycle-accurate and fast cycle-accurate) and one based on hardware acceleration.…”

“…FIGURE 11. MPSoC DSE, based on [123]. Different IP cores coexist in the MPSoC: some developed with HLS tools (IP1 and IP2) and others using RTL description.…”

Design Space Exploration of HW Accelerators and Network Infrastructure for FPGA-Based MPSoC

“…Many works provide tools that make it simple for system designers to compare several software and hardware options for executing the same algorithm [9] [17]. In [29], the authors take into consideration several HWAccs in an FPGA and their testbeds as input of the exploration algorithm. The result is a collection of dominant systems that trade off area and performance.…”