Design Space Exploration of Hardware Spiking Neurons for Embedded Artificial Intelligence

Abstract

A B S T R A C TMachine learning is yielding unprecedented interest in research and industry, due to recent success in many applied contexts such as image classification and object recognition. However, the deployment of these systems requires huge computing capabilities, thus making them unsuitable for embedded systems. To deal with this limitation, many researchers are investigating brain-inspired computing, which would be a perfect alternative to the conventional Von Neumann architecture based computers (CPU/GPU) that meet the requirements for computing performance, but not for energy-efficiency. Therefore, neuromorphic hardware circuits that are adaptable for both parallel and distributed computations need to be designed. In this paper, we focus on Spiking Neural Networks (SNNs) with a comprehensive study of information coding methods and hardware exploration. In this context, we propose a framework for neuromorphic hardware design space exploration, which allows to define a suitable architecture based on application-specific constraints and starting from a wide variety of possible architectural choices. For this framework, we have developed a behavioral level simulator for neuromorphic hardware architectural exploration named NAXT. Moreover, we propose modified versions of the standard Rate Coding technique to make trade-offs with the Time Coding paradigm, which is characterized by the low number of spikes propagating in the network. Thus, we are able to reduce the number of spikes while keeping the same neuron's model, which results in an SNN with fewer events to process. By doing so, we seek to reduce the amount of power consumed by the hardware. Furthermore, we present three neuromorphic hardware architectures in order to quantitatively study the implementation of SNNs. One of these architectures integrates a novel hybrid structure: a highly-parallel computation core for most solicited layers, and time-multiplexed computation units for deeper layers. These architectures are derived from a novel funnel-like Design Space Exploration framework for neuromorphic hardware.

Image Recognition and Simulation Based on Distributed Artificial Intelligence

“…Particle filtering obtains a huge swarm of particles through sampling technology, and iterative recursive operations are performed on each particle in the tracking process, which leads to a large increase in the calculation of the algorithm, and some particles also have particle degradation problems in the process. At present, on the basis of the particle filter algorithm, combined with the advantages of interactive multimodels to describe the motion characteristics of maneuvering targets, the researchers have proposed a particle filter algorithm based on interactive multimodels [20]. In the framework of interactive multimodels, multiple models are used to establish a mathematical model of highly maneuvering target motion, each of which describes all possible states of target motion.…”

RANC: Reconfigurable Architecture for Neuromorphic Computing

“…However, similar to NengoLoihi and NengoSpiNNaker, developing Nen-goRANC APIs in the future would enable co-design and execution of SNNs for user defined neuromorphic architectures in the RANC environment. Meanwhile, NAXT [49] provides an environment where users can generate FPGAbased SNN accelerators with a wide degree of flexibility in parameters of the generated architecture with regards to parallelism versus resource-usage tradeoffs. However, as NAXT is tailored specifically for SNN execution, the architectures it generates are specifically tailored for the baseline SNN architecture that is being mapped, and they are not suitable for use either by other SNNs with different architectures or non-machine learning applications in general.…”

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

“…Typical examples of such neuromorphic hardware implementing distributed computing include Intel's Loihi chip with 128 cores each having a local 2 MB static random access memory (SRAM) (Davies et al, 2018) and IBM's TrueNorth with 4096 neurosynaptic cores each containing 12.75 kB local SRAM (Merolla et al, 2014;Akopyan et al, 2015). Additionally, novel techniques such as time-multiplexing has been proposed to reduce hardware resources or facilitate memory usage efficiently (Akopyan et al, 2015;Davies et al, 2018;Wang et al, 2018;Abderrahmane et al, 2020). Further improvement in energy efficient on-chip training and inference can come from replacing digital SRAM arrays with high density analog synapses that can encode the synaptic weight directly using a physical property of the device such as conductance.…”