Design space exploration of cache memory — A survey

Upadhyay, Bhargavi R.; Sudarshan, T. S. B.

doi:10.1109/iceeot.2016.7755102

Cited by 5 publications

(3 citation statements)

References 20 publications

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“…We manually chose the cache parameters, such as the line size, number of lines, and so on, based on the array access patterns. However, there are multiple methods to automate the selection of these parameters, as attested by a large amount of past work, for example those analyzed by Upadhyay et al [22]. Integration of those approaches with our cache is left to future work.…”

Section: Discussionmentioning

confidence: 99%

“…We plan to automate the design space exploration for optimal cache parameter selection, by extending one of the state-of-the-art cache parameter optimization methods [22] to support the configuration space of our cache architecture for some additional dimensions with respect to standard caches, such as the request-response distance, the number of ports, and the address bit mapping.…”

Section: Discussionmentioning

confidence: 99%

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Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

et al. 2022

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Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories (block RAMs and registers). HLS tools allow exploiting the memory hierarchy in a scratchpad-like fashion, requring a significant manual effort. We propose an automation of the FPGA memory management in Xilinx Vitis HLS through a fullyconfigurable C++ source-level cache. Each DRAM-mapped array can be associated with a private level 2 (L2) cache with one or more ports, and each port can optionally provide a level 1 cache. The L2 cache runs in a separate dataflow task with respect to the application accessing it. This solution isolates off-chip memory accesses and data buffering into dedicated dataflow tasks, resembling the load, compute, store design paradigm, but without the drawback of manual algorithm refactoring. Experimental results collected from an FPGA board show that our cache speeds up the execution of a variety of benchmarks by up to 60 times compared to the out-of-the-box solution provided by HLS, requiring very limited optimization effort. Our caches are not meant to compete with manually optimized implementations quality of results (QoR), but rather to significantly save design effort, in exchange for some QoR, to make the HLS flow a bit more software-like, allowing the designer to focus on algorithmic optimizations, rather than on explicit memory management. Moreover, caching could be the only feasible memory optimization for algorithms with datadependent or irregular memory access patterns, but with good data locality.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

et al. 2022

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“…Pemilihan nilai atau teknik yang berbeda pada parameter-parameter perancangan cache memory sebagaimana dijelaskan diatas, dapat mempengaruhi kinerja dan konsumsi daya pada cache memory (Upadhyay 2016). Oleh karena itu untuk memilih konfigurasi terbaik dari sebuah cache maka diperlukan eksplorasi elemen-elemen perancangan cache.…”

Section: Ii3 Software Simulator Cache Memoryunclassified

Evaluasi Pengaruh Fungsi Pemetaan Terhadap Kinerja Dan Konsumsi Daya Cache Memory

Erlina

Putri

2017

jitter

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Menciptakan komputer yang berkinerja tinggi dan mengkonsumsi daya minimal merupakan salah satu fokus yang menjadi tren penelitian dalam bidang arsitektur komputer belakangan ini. Diketahui bahwa sejumlah faktor berpengaruh dalam menentukan kinerja dan konsumsi daya dari setiap elemen pembangun komputer dan pada akhirnya mempengaruhi kinerja dan konsumsi daya sebuah komputer secara keseluruhan. Fokus penelitian ini adalah untuk mengetahui seberapa besar pengaruh dari fungsi pemetaan (mapping techniques) sebagai salah satu jenis elemen perancangan yang diterapkan pada sebuah cache memory terhadap kinerja dan konsumsi daya dari cache memory dengan mensimulasikannya pada SMPCache dengan berbagai macam benchmark dan CACTI.[En]Creating high performance computers which consume minimal power is one of the focus and has become the trend of research in the field of computer architecture lately. It has been known that a number of factors influence the determination of the performance and power consumption of each of the building elements of the computer and ultimately affect the performance and overall power consumption of a computer. The focus of this research is to find out how much mapping functions as one of the type of design elements applied to a cache memory influence the performance and power consumption of the cache memory by simulating various configuration elements of the design in SMPCache with various benchmarks and CACTI.

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A Classification Model for Predicting Suitable Cache Level in a Multi-core Architecture

Thasneema

Bhaskaran

2021

2021 International Conference on Communication, Control and Information Sciences (ICCISc)

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Design space exploration of cache memory — A survey

Cited by 5 publications

References 20 publications

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Evaluasi Pengaruh Fungsi Pemetaan Terhadap Kinerja Dan Konsumsi Daya Cache Memory

A Classification Model for Predicting Suitable Cache Level in a Multi-core Architecture

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