Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC

Erdem, A.; Silvano, Cristina; Boesch, Thomas; Ornstein, Andrea C.; Singh, Surinder-Pal; Desoli, Giuseppe

doi:10.1109/asap.2018.8445096

Cited by 7 publications

(1 citation statement)

References 5 publications

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“…Yet, DCNNs are computationally heavy, in contrast with the latency requirements and power/energy constraints of embedded solutions. While the research focused on specialized accelerators Application Specific Integrated Circuits (ASICs) [1] or on FPGAs designs [2], these solutions do not "scale" to the application demands in that resources cannot be sized proportionally to the design size.…”

Section: Introductionmentioning

confidence: 99%

A Case Study for an Accelerated DCNN on FPGA-Based Embedded Distributed System

Nestorov

Scolari

Reggiani

et al. 2019

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Face Detection (FD) recently became the base of multiple applications requiring low latency but also with limited resources and energy budgets. Deep Convolutional Neural Networks (DCNNs) are especially accurate in FD, but latency requirements and energy budgets call for Field Programmable Gate Arrays (FPGAs)-based solutions, trading flexibility and efficiency. Nonetheless, the offer of FPGAs solutions is limited and different chips often require expensive redesign phases, while developers desire solutions whose resources can scale proportionally to the demands. Therefore, this work presents an FD solution based on a DCNN on a distributed, embedded system with FPGAs, proposing a general approach to reduce the DCNN size and to design its FPGA cores and investigating its accuracy, performance, and energy efficiency.

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Section: Introductionmentioning

confidence: 99%