Design space exploration for 3D-stacked DRAMs

Weis, Christian; Wehn, Norbert; Loi, Igor; Benini, Luca

doi:10.1109/date.2011.5763068

Cited by 55 publications

(37 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…DSE for 3D-stacked DRAMs by Weis et al Design space exploration for 3D-stacked DRAMs has been developed by Weis et al [39]. They defined a 3D-DRAM based on a SystemC model with a 3D channel controller and also considered a wiring model for the TSVs.…”

Section: D-sic Toolsmentioning

confidence: 99%

Multi-objective optimization and multi-criteria decision aid applied to the design of 3D-stacked integrated circuits

Doan¹

2016

4OR-Q J Oper Res

View full text Add to dashboard Cite

Section: D-sic Toolsmentioning

confidence: 99%

Multi-objective optimization and multi-criteria decision aid applied to the design of 3D-stacked integrated circuits

Doan¹

2016

4OR-Q J Oper Res

View full text Add to dashboard Cite

“…In case of NAND flash memory, when the cells are smaller than 20 nm, it is no longer costeffective as the cost of patterning is too large. Due to these reasons, V-NAND Flash and 3D-DDR3 DRAM attempt to scale the capacity by leveraging the 3D stacking technology rather than scaling down the chip size [7,8]. In contrast, it is expected that PCM will have stable characteristics in 5 nm node [9].…”

Section: Phase-change Memory Technologiesmentioning

confidence: 99%

A Working-set Sensitive Page Replacement Policy for PCM-based Swap Systems

Park¹,

Bahn²

2017

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-Due to the recent advances in PhageChange Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

show abstract

“…978-3-9810801-8-6/DATE12/ c 2012 EDAA A design-space exploration of 3D-stacked DRAM architectures with respect to performance, energy, and area efficiency for different memory densities is performed in [15]. In [16] and [17], an average-case analysis of off-chip multi-channel memories is performed to evaluate the performance of multiple memory channels offered by 3D-stacked DRAMs.…”

Section: Related Workmentioning

confidence: 99%

“…To evaluate the performance impact of the memory interface width, we consider 16, 32, 64, and 128-bit devices. Note that 64-bit interface devices are not included in the Wide-IO specifications, but have been generated using the 3D-DRAM generator in [15] to understand the impact of interface width on performance and power consumption. The BL is reduced as the interface width increases to keep the same access granularity for all devices.…”

Section: A Preconditionsmentioning

confidence: 99%

“…From LPDDR to LPDDR2, operating frequency has been increased to provide higher bandwidth, and supply voltage has been reduced for lower power consumption. The JEDEC Wide-IO draft specification states that a 3D-DRAM device consists of 4 independent channels, each having interface width of 128 bits [6] and operates at 1.2 V. The speeds of 3D-DRAMs in Table I are selected based on the chosen technology and architecture using the 3D-DRAM generator presented in [15].…”

Section: Mobile Dram Generationsmentioning

confidence: 99%

See 1 more Smart Citation

DRAM selection and configuration for real-time mobile systems

Gomony¹,

Weis²,

Åkesson³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Abstract-The performance and power consumption of mobile DRAMs (LPDDRs) depend on the configuration of system-level parameters, such as operating frequency, interface width, request size, and memory map. In mobile systems running both realtime and non-real-time applications, the memory configuration must satisfy bandwidth requirements of real-time applications, meet the power consumption budget, and offer the best averagecase execution time to the non-real-time applications. There is currently no well-defined methodology for selecting a suitable memory configuration for real-time mobile systems. The worstcase bandwidth, average-case execution time, and power consumption of mobile DRAMs across generations have furthermore not been investigated. This paper has two main contributions. 1) We analyze the worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across three generations: LPDDR, LPDDR2 and Wide-IO-based 3D-stacked DRAM. 2) Based on our analysis, we propose a methodology for selecting memory configurations in real-time mobile systems. We show that LPDDR (32-bit IO), LPDDR2 (32-bit IO) and 3D-DRAM (128-bit IO) provide worst-case bandwidth up to 0.75 GB/s, 1.6 GB/s and 3.1 GB/s, respectively. We furthermore show for an H.263 decoder that LPDDR2 and 3D-DRAM reduce power consumption with up to 25% and 67%, respectively, compared to LPDDR, and reduce the execution time with up to 18% and 25%.

show abstract

Design space exploration for 3D-stacked DRAMs

Cited by 55 publications

References 9 publications

Multi-objective optimization and multi-criteria decision aid applied to the design of 3D-stacked integrated circuits

Multi-objective optimization and multi-criteria decision aid applied to the design of 3D-stacked integrated circuits

A Working-set Sensitive Page Replacement Policy for PCM-based Swap Systems

DRAM selection and configuration for real-time mobile systems

Contact Info

Product

Resources

About