Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

Spin-transfer torque random access memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/9 ∼ 1/3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. However, deploying STT-RAM technology in L1 caches is challenging because of the long and power-consuming write operations. In this paper, we propose both L1 and lower level cache designs that use STT-RAM. In particular, our designs use STT-RAM cells with various data retention time and write performances, made possible by different magnetic tunneling junction (MTJ) designs. For the fast STT-RAM bits with reduced data retention time, a counter controlled dynamic refresh scheme is proposed to maintain the data validity. Our dynamic scheme saves more than 80% refresh energy compared to the simple refresh scheme proposed in previous works. A L1 cache built with ultra low retention STT-RAM coupled with our proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy when compared to one that uses traditional SRAM. For lower level caches with relative large cache capacity, we propose a data migration scheme that moves data between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. Our experiments show that on the average, our proposed multi retention level STT-RAM cache reduces 30 ∼ 70% of the total energy compared to

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“…The required switching current density, JC , of a MTJ operating in different working regions can be approximated as [19,16]:…”

Section: Mtj Write Performance Vs Nonvolatilitymentioning

confidence: 99%

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Sun

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

191

156

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“…Based on the experimental and theoretical studies, the critical current density (J c0 ) for MTJ switching can be calculated as [23]:…”

Section: Intrinsic Asymmetry Of the Stt Effectmentioning

confidence: 99%

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Liu

Zhang

et al. 2017

IEICE Electron. Express

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Non-volatile memories (NVMs), such as Magnetic RAM and Resistive RAM, have been considered as the potential working or storage memories in the next generation computer architectures, thanks to the various merits, such as non-volatility, low power and high speed etc. However, new technology brings simultaneously new challenges, e.g. reliability issue, before practical applications. Compared with conventional memories, the errors in NVMs are generally asymmetric, resulting in different failure rates for 0-1 and 1-0 bit flipping. Error correcting codes (ECCs) are common solutions for protecting memories from errors. The most widely used ECCs are the single error correction and double error detection (SEC-DED) codes. Unfortunately, they are primarily designed for correcting symmetric errors and their error correction capabilities are limited to only one bit. Regarding the failure characteristics (e.g., multi-bit and asymmetric) of NVMs, conventional SEC-DED codes are not efficiently applicable. This paper proposes an extended coset decoding scheme for NVMs. Our simulation results with a Hamming code (with Hamming distance of only three) as an example show the effectiveness of the proposed decoding scheme. The proposed decoding scheme can also be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.

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“…The average current required for switching (I therm C ) depends on the write pulse duration (T wr ). The following deterministic model is often used to describe this relationship, despite the inherent stochasticity of the write process [8]:…”

Section: A Stt-ram Write Processmentioning

confidence: 99%

“…where ∆ is the thermal stability factor [8], [9]. The second mechanism, fast precession switching, is very rapid, typically occurring within 1ns, and shows less stochasticity.…”

Section: A Stt-ram Write Processmentioning

confidence: 99%

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Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Zheng

Park

Orshansky

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worstcase duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3% − 99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.

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Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

Cited by 110 publications

References 3 publications

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

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