Design-Silicon Timing Correlation A Data Mining Perspective

Wang, Li-C.; Bastani,; Abadir,

doi:10.1109/dac.2007.375193

Cited by 9 publications

(4 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [9], post-silicon measurements are used to learn a more accurate spatial correlation model to refine the SSTA framework. A path-based methodology is proposed in [10] to correlate post-silicon test data to presilicon timing analysis. In [11], a statistical gate sizing approach is presented to optimize the binning yield.…”

Section: Introductionmentioning

confidence: 99%

Capturing Post-Silicon Variations Using a Representative Critical Path

Liu

Sapatnekar

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-In nanoscale technologies that experience large levels of process variation, post-silicon adaptation is an important step in circuit design. These adaptation techniques are often based on measurements on a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit after manufacturing. For realistic circuits, where the number of critical paths can be large, the notion of using a single critical path is too simplistic. This paper overcomes this problem by introducing the idea of synthesizing a representative critical path (RCP), which captures these complexities of the variations. We first prove that the requirement on the RCP is that it should be highly correlated with the circuit delay. Next, we present three novel algorithms to automatically build the RCP. Our experimental results demonstrate that over a number of samples of manufactured circuits, the delay of the RCP captures the worst case delay of the manufactured circuit. The average prediction error of all circuits is shown to be below 2.8% for all three approaches. For both our approach and the critical path replica method, it is essential to guard-band the prediction to ensure pessimism: on average our approach requires a guard band 31% smaller than for the critical path replica method.

show abstract

Section: Introductionmentioning

confidence: 99%

Capturing Post-Silicon Variations Using a Representative Critical Path

Liu

Sapatnekar

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Bastani et al [1]- [3] and Wang et al [12] pioneered machinelearning-based approaches that use path delay measurements. They try to find a relation between path delay measurements and design features directly.…”

Section: Introductionmentioning

confidence: 99%

Segment Delay Learning From Quantized Path Delay Measurements

Chung

Kim

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Our understanding on a silicon chip is limited due to low measurement resolution or model-silicon miscorrelation including variations. This paper shows that chips are better understood by combining noisy measurement results and model information through a mathematical algorithm. Our proposed method learns segment delays in logic circuits from quantized path delay measurements using ridge regression. During the learning process, we take advantage of both nominal segment delays and the delay sensitivity with respect to variations. We also interpret the ridge regression in Bayesian context and in doing so, propose an analytic formula to set the regularization parameter of the ridge regression. For the silicon measurement environments where low measurement resolution is the dominant source of measurement noise, this formula allows us to predict post-silicon results more accurately and speed up the algorithm eliminating inefficient and inaccurate cross-validation. We also demonstrate our method in enhancing the resolution of already measured path delays. We learn segment delays from quantized path delay measurements and predict the path delays prior to the quantization. Our simulation results show that the predicted path delays are much closer to actual values than the measured values and the nominal values.Index Terms-Defect diagnosis, machine learning, post-silicon debug, post-silicon validation.

show abstract

“…In [48], postsilicon measurements are used to learn a more accurate spatial correlation model, which is fed back to the analysis stage to refine the statistical timing analysis framework. In [49], a pathbased methodology is used for correlating post-silicon test data to presilicon timing analysis. In [50], a statistical gate sizing approach is studied to optimize the binning yield.…”

Section: Post-silicon Sensor Measurementsmentioning

confidence: 99%

Overcoming Variations in Nanometer-Scale Technologies

Sapatnekar

2011

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

Abstract-Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and enviromental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.

show abstract

Design-Silicon Timing Correlation A Data Mining Perspective

Cited by 9 publications

References 0 publications

Capturing Post-Silicon Variations Using a Representative Critical Path

Capturing Post-Silicon Variations Using a Representative Critical Path

Segment Delay Learning From Quantized Path Delay Measurements

Overcoming Variations in Nanometer-Scale Technologies

Contact Info

Product

Resources

About