2007
DOI: 10.1109/dac.2007.375193
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Design-Silicon Timing Correlation A Data Mining Perspective

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Cited by 9 publications
(4 citation statements)
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“…In [9], post-silicon measurements are used to learn a more accurate spatial correlation model to refine the SSTA framework. A path-based methodology is proposed in [10] to correlate post-silicon test data to presilicon timing analysis. In [11], a statistical gate sizing approach is presented to optimize the binning yield.…”
Section: Introductionmentioning
confidence: 99%
“…In [9], post-silicon measurements are used to learn a more accurate spatial correlation model to refine the SSTA framework. A path-based methodology is proposed in [10] to correlate post-silicon test data to presilicon timing analysis. In [11], a statistical gate sizing approach is presented to optimize the binning yield.…”
Section: Introductionmentioning
confidence: 99%
“…Bastani et al [1]- [3] and Wang et al [12] pioneered machinelearning-based approaches that use path delay measurements. They try to find a relation between path delay measurements and design features directly.…”
Section: Introductionmentioning
confidence: 99%
“…In [48], postsilicon measurements are used to learn a more accurate spatial correlation model, which is fed back to the analysis stage to refine the statistical timing analysis framework. In [49], a pathbased methodology is used for correlating post-silicon test data to presilicon timing analysis. In [50], a statistical gate sizing approach is studied to optimize the binning yield.…”
Section: Post-silicon Sensor Measurementsmentioning
confidence: 99%