Design risk for fabrication stability of silicon single-photon avalanche diodes with deep N-well implantation

Abstract

Single-photon avalanche diodes (SPADs) are high-performance light-sensitive sensors operating in low-light condition. Si-SPADs manufactured through standard CMOS fabrication process have advantages in terms of manufacturing cost, low power consumption, device shrinkage, and process stability compared to SPADs on custom fabrication. A deeper multiplication using deep n-well (DNW) improves key performances of Si-SPAD such as dark count rate (DCR) and photon detection efficiency (PDE). Here, the guard ring (GR) must be included for deep junction SPAD because light detection efficiency is lowered due to premature edge breakdown (PEB) generated by strong electric field at the edge. PEB affects not only the characteristics but also the manufacturing uniformity. Therefore, the DNW should be carefully designed to show better performance and stability for Si-SPADs. In this paper, the effects of electrical characteristics such as current-voltage (I-V) curve, DCR, off leakage, and breakdown voltage, and process stability on DNW implanted SPAD with GR variation are analyzed using actual fabricated SPAD measurement data and the calibrated technology computer-aided design (TCAD) simulated results. When the deep multiplication junction is formed using the higher ion implantation energy, the penetration effect and the process instability can be generated and it can also weaken the GR effect, which prevents PEB caused by having a stronger electric field than the multiplication zone. In addition, it is verified to prevent the risk of designing a Si-SPAD and die-to-die variation due to DNW implantation. Based on the results, deep junction design scheme for high resolution and mass production can be suggested.