Design optimization of wiring substrate in a CMOS-based multichip module

Sudo, Takashi; Hirano, N.; Kato, Keizo; Hiruta, Y.; Fuchida, Y.

doi:10.1109/ectc.1992.204282

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…They are the MCM-Si, MCM-C, MCM-D, and MCM-L types [3] [4]. The selection of an optimal packaging type requires t he consideration from the viewpoints of both performance and cost [ 5 ] . For high clock operation, it has become more and more important to control the signal fluctuation as well as to reduce the interconnect delay.…”

Section: Introductionmentioning

confidence: 99%

Characterization of net configurations for multichip modules

Okada

Sudô

Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)

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An investigation of the design considerations for MCMs based on CMOS VLSI has been carried out with the aim of achieving a higher performance system. Included in the investigation were output driver and receiver characteristics and net configurations in MCM. Four MCM types have been introduced: MCM-D, MCM-Si, MCM-C, and MCM-L. Time domain analysis using the SPICE simulation program was carried out taking into consideration a lossy transmission line model. A simpler criterion for the critical damping condition and an estimation method for the signal delay of the network with a lumped circuit approximation is proposed to determine a preferable interconnect network including the output driver and the loads. The effect of the net configuration was also analyzed and the preferences among the net configurations have been represented with only two net parameters such as the total net length and the far-end length.

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Section: Introductionmentioning

confidence: 99%

Characterization of net configurations for multichip modules

Okada

Sudô

Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)

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Resistive signal line wiring net designs in multichip modules

Chang¹

1993

IEEE Trans. Comp., Hybrids, Manufact. Technol.

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Resistive signal line wiring net designs in multichip modules

Chang¹

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)

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To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, we propose formulas with one pole and one zero on the negative real axis. W e then derive the algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source. either open circuited or terminated by a constant resistance load. Nomographs to guide the MCM wiring net designs are also developed and presented.The far-end of this line is

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Design optimization of wiring substrate in a CMOS-based multichip module

Cited by 4 publications

References 9 publications

Characterization of net configurations for multichip modules

Characterization of net configurations for multichip modules

Resistive signal line wiring net designs in multichip modules

Resistive signal line wiring net designs in multichip modules

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