2020
DOI: 10.1109/ted.2020.2986536
|View full text |Cite
|
Sign up to set email alerts
|

Design Optimization of Photovoltaic Cell Stacking in a Triple-Well CMOS Process

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2021
2021
2023
2023

Publication Types

Select...
4

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 12 publications
0
2
0
Order By: Relevance
“…This is well within the capabilities of silicon technology where pn/pn junctions are regularly made with triple-well CMOS processes. Triple-well processes were already used to integrate solar harvesters into self-powered circuits [34], [35]. However, the goal of these efforts was not to develop tandem cells but to provide a harvester as add-on to the circuit.…”
Section: Manufacturabilitymentioning
confidence: 99%
See 1 more Smart Citation
“…This is well within the capabilities of silicon technology where pn/pn junctions are regularly made with triple-well CMOS processes. Triple-well processes were already used to integrate solar harvesters into self-powered circuits [34], [35]. However, the goal of these efforts was not to develop tandem cells but to provide a harvester as add-on to the circuit.…”
Section: Manufacturabilitymentioning
confidence: 99%
“…However, the goal of these efforts was not to develop tandem cells but to provide a harvester as add-on to the circuit. Consequently, the dopant profiles were not necessarily ideal for efficient solar cells [34] and only the upper junction was used for a solar cell in single-junction configuration, whereas the underlying junction served to separate the cell from the circuitry [35].…”
Section: Manufacturabilitymentioning
confidence: 99%