Design Optimization of CML-Based High-Speed Digital Circuits

Abstract

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.