Design optimization in write speed of multi-level cell application for phase change memory

Lin, Jun-Tin; Liao, Yunlong; Chiang, Meng-Hsueh; Chiu, I-Hsuan; Lin, Chia-Long; Hsu, Wei‐Chou; Chiang, Pei-Chia; Sheu, Shyh-Shyuan; Hsu, Yu‐I; Liu, Wen-Hsing; Su, Keng-Li; Kao, Ming-Jer; Tsai, Ming-Jinn

doi:10.1109/edssc.2009.5394196

2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2009

DOI: 10.1109/edssc.2009.5394196

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Design optimization in write speed of multi-level cell application for phase change memory

Jun-Tin Lin

Yunlong Liao

Meng-Hsueh Chiang

et al.

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Design optimization in write speed of multi-level cell application for phase change memory

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