Design of Vedic Multiplier Using Reversible Logic Gates

Awade, Anirudh; Jain, Prachi; Hemavathy, S; Bhaaskaran, V. S. Kanchana

doi:10.1007/978-981-15-9019-1_38

Cited by 1 publication

(3 citation statements)

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“…However, increasing the inputs' size in the Vedic multiplier does not increase the multiplication process latency [5]. Moreover, Vedic multipliers improve the performance concerning the processing time because they require fewer adders than other multiplication methods [13].…”

Section: × 4 Vedic Multipliermentioning

confidence: 99%

“…Finally, use three 4-bits binary adders to add the partial products, as shown in Fig. 2 [1,13]. The second approach uses the UT sutra directly shown in Fig.…”

Section: × 4 Vedic Multipliermentioning

confidence: 99%

“…The reduction was only a quantum cost of 2 (from 162 of the literature design to 160). Awade et al [13] provided a comparative study between three designs for 8 × 8 reversible. Each of them was implemented using different adders to study the impact of adder type on the multiplier circuit.…”

Section: Adder Compressorsmentioning

confidence: 99%

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Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

Elmenyawi¹,

Tawfeek²

2023

Computer Systems Science and Engineering

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One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two's complement (B2C) and MUX circuits, while DesignII combines binary two's complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-ofthe-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

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Section: × 4 Vedic Multipliermentioning

confidence: 99%

“…Finally, use three 4-bits binary adders to add the partial products, as shown in Fig. 2 [1,13]. The second approach uses the UT sutra directly shown in Fig.…”

Section: × 4 Vedic Multipliermentioning

confidence: 99%