Design of variable-rate irregular LDPC codes with low error floor

Dinoi, Libero; Benedetto, S.

doi:10.1109/icc.2005.1494431

Cited by 25 publications

(11 citation statements)

References 15 publications

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“…Nonetheless, practical implementation generally re uires short-to-moderate n <10 and efficien code representation. Two major approaches of designing good finite codes consist of systematically searching through the random code ensemble or directly constructing codes under combinatorial/algebraic guidelines [1] [2] The former ap proach is best represented by the progressive edge growth (PEG) construction in which greedy/trellis based algorithms for edge assignment have been proposed with different objective functions such as the girth [3], the extrinsic cycle degree [4], partial elimination of stopping sets [5], further criteria regarding degree 2 variable nodes [6], and the averaged error rate upper bound [7].…”

Section: Introduction and The Main Resultsmentioning

confidence: 99%

Code Annealing and the Suppressing Effect of the Cyclically Lifted LDPC Code Ensemble

Wang

2006

2006 IEEE Information Theory Workshop - ITW '06 Chengdu

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Code annealing, a new method of designing good codes of short block length, is proposed, which is then concatenated with cyclic lifting to create finite codes of low frame error rate (FER) error floors without performance outliers. The stopping set analysis is performed on the cyclically lifted code ensemble assuming uniformly random lifting sequences, and the suppressing effect/weight of the cyclic lifting is identified for the first time, based on which the ensemble FER error floor can be analytically determined and a scaling law is derived. Both the first-order and high-order suppressing effects are discussed and quantified by different methods including the explicit expression, an algorithmic upper bound, and an algebraic lower bound.The mismatch between the suppressing weight and the stopping distances explains the dramatic performance discrepancy among different cyclically lifted codes when the underlying base codes have degree 2 variable nodes or not. For the former case, a degree augmentation method is further introduced to mitigate this metric mismatch, and a systematic method of constructing irregular codes of low FER error floors is presented. Both regular and irregular codes of very low FER error floors are reported, for which the improvement factor ranges from 106_104 when compared to the classic graph-based code ensembles.

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Section: Introduction and The Main Resultsmentioning

confidence: 99%

Code Annealing and the Suppressing Effect of the Cyclically Lifted LDPC Code Ensemble

Wang

2006

2006 IEEE Information Theory Workshop - ITW '06 Chengdu

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“…In Reference [61], a new deterministic and straightforward rule to extend the parity-check matrix of extended IRA codes was devised: Each row of the mother code is mapped into two adjacent rows of the extended code. This technique, other than being very simple and easy to implement, preserves also the properties of the original code, such as girth and other parameters related to the cycle structure, shown in Reference [59] to be crucial for the code performance.…”

Section: Code-rate Versatilitymentioning

confidence: 97%

“…The work in Reference [59] took inspiration from this fact to provide a very easy rule to design puncturing patterns for rate-compatible extended IRA codes; a very similar approach for an affine category of LDPC codes was described in Reference [60]. The approach in Reference [59] is based on an alternate puncturing pattern; due to the structure of the parity-check VNs of extended IRA codes, this guarantees that there are no CNs connected to two punctured VNs.…”

Section: Code-rate Versatilitymentioning

confidence: 98%

“…The approach in Reference [59] is based on an alternate puncturing pattern; due to the structure of the parity-check VNs of extended IRA codes, this guarantees that there are no CNs connected to two punctured VNs. This rather conservative rule (under a precise analysis of the specific parity-check matrix it could be possible also to allow a small fraction of CNs connected to multiple punctured VNs) has the shortcoming of permitting only a limited, even if quite large, variation of code rate, so that it may be necessary to employ a few mother codes to support all the needed code rates.…”

Section: Code-rate Versatilitymentioning

confidence: 99%

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Design issues in the implementation of versatile, high‐speed iterative decoders

Benedetto

Dinoi

Montorsi

et al. 2007

Trans Emerging Tel Tech

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SUMMARYThe ever increasing demand for high data rate communication, and the use of radio resource management techniques requiring frame-by-frame adaptive coding/modulation to match user demands and channel conditions, pose a number of crucial problems to the design of versatile, high-speed iterative decoders, for both turbo-like and low-density parity-check codes. Among them, we mention:The modification of the Soft-Input Soft-Output (SISO) algorithm in a way that permits its implementation using several parallel processors working independently on segments of the received frame. The collisions in the process of reading/writing into/from the memory by the parallel processors. The design of prunable interleavers covering a wide range of information and/or code words lengths while keeping good spreading properties. The design of codes yielding a wide range of code rates with good performance for the range of probability of error of interest.The paper will touch all the previous points, offering state-of-the art solutions and examples showing their performance.

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“…While the VN and CN degree distributions determine the convergence behavior of the code asymptotically (for an infinite block length), the actual structure of the parity-check matrix is crucial for the performance of finite length LDPC codes. Many design algorithms can be applied to obtain a good parity-check matrix [18][19][20]; specific design algorithms for eIRA codes are presented in [21,22].…”

Section: Ldpc and Eira Codes Backgroundmentioning

confidence: 99%

Design of a VLSI Decoder for Partially Structured LDPC Codes

Vacca

Dinoi

Masera

2008

International Journal of Digital Multimedia Broadcasting

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The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edges of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

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Design of variable-rate irregular LDPC codes with low error floor

Cited by 25 publications

References 15 publications

Code Annealing and the Suppressing Effect of the Cyclically Lifted LDPC Code Ensemble

Code Annealing and the Suppressing Effect of the Cyclically Lifted LDPC Code Ensemble

Design issues in the implementation of versatile, high‐speed iterative decoders

Design of a VLSI Decoder for Partially Structured LDPC Codes

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