“…This is due to the fact that band gap of Si 1−x Ge x decreases with increasing Ge composition. Since the highest Ge composition of Si 1−x Ge x is around 40% in industrial production [9], the Ge composition x = 0.3 is regarded as the optimal Ge composition parameter in all the simulations. And Si 0.7 Ge 0.3 pocket can help HTG-TFET to obtain the not only higher on-state current but also lower off-state current.Fig.…”
In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V
g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V
g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.
“…This is due to the fact that band gap of Si 1−x Ge x decreases with increasing Ge composition. Since the highest Ge composition of Si 1−x Ge x is around 40% in industrial production [9], the Ge composition x = 0.3 is regarded as the optimal Ge composition parameter in all the simulations. And Si 0.7 Ge 0.3 pocket can help HTG-TFET to obtain the not only higher on-state current but also lower off-state current.Fig.…”
In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V
g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V
g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.
“…However, there are also inherent disadvantages in TFETs, the most serious problems are small ON-state current and large miller capacitance. To address these issues, a lot of novel structures of TFETs are proposed [8][9][10][11][12][13][14][15][16][17][18][19]. As a whole, most of TFETs reported in recent years adopt different doping concentration in channel and active regions to form heavily doped abrupt junction at tunneling interface, which leads to a complex fabrication processes and a high thermal budget, what's more, introduction of high-density layer at source/channel junction and Gaussian doping in drain region also find difficultly during fabrication process and it's easy to be influenced by random dopant fluctuations (RDFs) [20][21][22][23].…”
In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions Φ M1 , Φ M2 and Φ M3 , respectively, where Φ M1 = Φ M3 < Φ M2 . Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 10 −6 A/µm, and the maximum g m (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 10 −5 S/µm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (f T ) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum f T of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.
“…are proposed for effective gate control and to improve tunneling probability [1]. Likewise, various silicon germanium hereto-structures such as L-shaped [15], U-shaped [16], etc. are proposed for enhanced ON current, but such elevated TFET structures are very challenging in terms of fabrication.…”
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