Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

“…where GBW = βa 0 ω d = βG m1 /C C1 the gain-bandwidth product of the OTA. Finally, assuming the usual and convenient constraint G mf = G m3 [51,60], the remaining coefficients are:…”

“…The stability of the amplifier can be achieved using the global separation factors introduced in [60] and used in [61,62]. Without going into theoretical detail, our three-stage OTA can be considered as a feedback circuit with two nested loops, each of which must be frequency compensated.…”

“…Recently, in [60,63], the authors obtained an approximated but useful design equation that estimates the settling time when slew-rate limitations occur in the first stage of the amplifier. With respect to the small-signal settling time, t s0 , the settling time under slew-rate limitations is:…”

“…The design equation in ( 21) is valid if the slew-rate limitation resides in the first stage. If this condition is not satisfied, the amplifier can experience a positive feedback connection during its slewing period that leads to large overshoots and degrades the settling-time performance [60,64]. To prevent this situation, as usually done in sub-threshold OTAs, slew-rate enhancers [65][66][67][68] or class-AB topologies [26,[69][70][71] must be used for the stages after the first one.…”

Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints

“…Modeling the output impedance of the OTA as in (5), the closed-loop amplifier can be modeled with the block schematic in Fig. 1a where, for the single-pole case, ( ) = 1 [17].…”