Design of RM-nc: a reconfigurable neurocomputer for massively parallel-pipelined computations

Erdogan, S.S.; Wahab, Abdul

doi:10.1109/ijcnn.1992.226988

Cited by 7 publications

(4 citation statements)

References 10 publications

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“…Another example of a system optimized for a specific task is the RM-nc system [Erdogan92]. As shown in Figure 19, the system has a controller chip A, and two linear arrays of FPGAs B-E and F-I.…”

Section: Multi-fpga Systemsmentioning

confidence: 99%

The roles of FPGAs in reprogrammable systems

Hauck

1998

Proc. IEEE

278

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FPGA-based reprogrammable systems are revolutionizing some forms of computation and digital logic. As a logic emulation system they provide orders of magnitude speedup over software simulation. As a custom-computing machine they achieve the highest performance implementation for many types of applications. As a multi-mode system they yield significant hardware savings and provide truly generic hardware. In this paper we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems, as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.

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Section: Multi-fpga Systemsmentioning

confidence: 99%

The roles of FPGAs in reprogrammable systems

Hauck

1998

Proc. IEEE

278

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“…• Digital neurocomputers can be considered the massively data-parallel computers. Several neurocomputers are: WARP (Arnould 1985, Kung and Webb 1985, Annaratone et al 1987, CM (Means and Hammerstrom 1991), RAP (Morgan et al 1990, Beck 1990), SANDY (Kato et al 1990), MUSIC (Gunzinger et al 1992, Müller et al 1995, MIND (Gamrat et al 1991), SNAP (Hecht-Nielsen 1991, Means and Lisenbee 1991), GF-11 (Witbrock andZagha 1990, Jackson and, Toshiba (Hirai 1991), MANTRA Blayo 1991, Lehmann et al 1993), SYNAPSE (Ramacher 1992, Ramacher et al 1991a, Johnson 1993a, HANNIBAL (Myers et al 1993), BACCHUS and PAN IV (Huch et al 1990, Palm and Palm 1991, PANNE (Milosavlevich et al 1996), 128 PE RISC (Hiraiwa et al 1990), RM-nc256 (Erdogan and Wahab 1992), CNAPS (Adaptive Solutions 1991, Hammerstrom 1990 Digital integrated circuit implementations 1990, Yasunaga et al 1989Yasunaga et al -1991, MasPar MP-1 (Grajski et al 1990, MasPar 1990a-c, Nickolls 1990, and CNS-1 (Asanović et al 1993a)-just to mention only the most well-known.…”

Section: Beiu Et Almentioning

confidence: 99%

“…• The RM-nc is a reconfigurable machine for massively parallel-pipelined computations and has been proposed in Erdogan and Wahab (1992). The reconfigurability is not only in the domain of communication and control, but also in the domain of processing elements.…”

mentioning

confidence: 99%

Digital integrated circuit implementations

Beiu¹

Handbook of Neural Computation

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This section considers some of the alternative approaches towards modeling biological functions by digital circuits. It starts by introducing some circuit complexity issues and arguing that there is considerable computational and physiological justification that shallow threshold gate circuits are computationally more efficient than classical Boolean circuits. We comment on the tradeoff between the depth and the size of a threshold gate circuit, and on how design parameters like fan-in, weights and thresholds influence the overall area and time performances of a digital neural chip. This is followed by briefly discussing the constraints imposed by digital technologies and by detailing several possible classification schemes as well as the performance evaluation of such neurochips and neurocomputers. Lastly, we present many typical and recent examples of implementation and mention the 'VLSI-friendly learning algorithms' as a promising direction of research.

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“…Example of a multi-FPGA topology that cannot be handled by sequential placement techniques, but which can be found in current systems[20,7,14,6,21].…”

mentioning

confidence: 99%

Pin assignment for multi-FPGA systems

Hauck

Borriello

Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines

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There is currently great interest in using systems of FPGAs for logic emulators, custom computing devices, and software accelerators. An important step in making these technologies more generally useful is to develop completely automatic mapping tools from high-level specification to FPGA programming files. In this paper we examine one step in this automatic mapping process, the selection of FPGA pins to use for routing inter-FPGA signals. We present an algorithm that greatly increases mapping speed while also improving mapping quality.

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Design of RM-nc: a reconfigurable neurocomputer for massively parallel-pipelined computations

Cited by 7 publications

References 10 publications

The roles of FPGAs in reprogrammable systems

The roles of FPGAs in reprogrammable systems

Digital integrated circuit implementations

Pin assignment for multi-FPGA systems

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