Design of Risc Processor Using VHDL

Kadam, S.; Mali, S. D.

doi:10.29121/granthaalayah.v4.i6.2016.2646

Cited by 3 publications

(2 citation statements)

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“…Modeling various processor architectures in hardware description languages has been extensively explored in the past for both research and educational purposes [36][37][38][39][40][41][42][43][44][45][46]. The main objective is either developing an open-source application-specific processor (like [42]) or accelerating computer architecture learning process.…”

Section: Evaluation Process and Discussion Of The Resultsmentioning

confidence: 99%

Project-Based Learning and Evaluation in an Online Digital Design Course

Skliarova

2021

Electronics

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This paper reports an experience of an abrupt shift from traditional teaching to distance learning within a course on digital system design using programmable logic platforms. The course organization and evaluation model had to be modified on the fly due to the COVID-19 pandemic. The adopted teaching and assessment methodology puts a strong focus on the laboratory component, assigning a very significant weight to project-based evaluation. As the access to laboratory equipment was cut, all the previously accumulated experience had to be modified and adapted to new circumstances. The paper discusses teaching methods employed within the course and analyzes in detail a project-based evaluation accentuated on modeling of a simplified processor. The advantages and drawbacks of the reported teaching methods are appointed. Possible design extensions are also suggested, which permit assigning the same core project to different students. We believe that the proposed project is a valuable instructional tool, in particular, for remote learning/assessment.

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Section: Evaluation Process and Discussion Of The Resultsmentioning

confidence: 99%

Project-Based Learning and Evaluation in an Online Digital Design Course

Skliarova

2021

Electronics

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“…A from top to down approach is preferred in the design. 16-bit RISC processor design is presented using the VHDL language [16]. The design is simulated and synthesized using Xilinx ISE 13.1.…”

Section: Introductionmentioning

confidence: 99%

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

Ozkilbac

Karacalı

2022

Erzincan Üniversitesi Fen Bilimleri Enstitüsü Dergisi

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The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

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Designing of 32-Bit Configurable Hack CPU On FPGA

Kawle

Thakare

2021

2021 6th International Conference on Communication and Electronics Systems (ICCES)

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Design of Risc Processor Using VHDL

Cited by 3 publications

References 3 publications

Project-Based Learning and Evaluation in an Online Digital Design Course

Project-Based Learning and Evaluation in an Online Digital Design Course

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

Designing of 32-Bit Configurable Hack CPU On FPGA

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