Design of RF Prototype for the Energy Harvesting System

Yedidiah, R. Larkin; Kumar, K.J. Jegadish

doi:10.1109/iccsp.2018.8524197

Cited by 2 publications

(2 citation statements)

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“…path with rectifiers utilizing DC-boosted gate bias and internal body bias, respectively. Instead of using discrete Schottky diode in [51], [81] and [82] to lower the diode forward voltage drop, the proposed low-power rectifier employs DC-boosted gate bias to compensate the transistor's V th . [70] and [83] focuses on design optimization methodology for conventional cross-coupled rectifier, with [83] using discrete MPPT PMU to boost and regulate V OUT .…”

Section: Measurement Setupmentioning

confidence: 99%

“…However, considering the relatively large coupling capacitors used and dummy capacitors placed on layout to mitigate process impact, it is comparable to prior works. APMC '17 [51] TMTT '19 [81] ICCSP '18 [82] ICECS '16 [70] JSSC '19 [83] TCAS '17 [84] This work TMTT '19 [81] ICCSP '18 [82] ICECS '16 [70] JSSC '19 [83] TCAS '17 [84] This work TMTT '19 [81] ICCSP '18 [82] ICECS '16 [70] JSSC '19 [83] TCAS '17 [84] This work Conjugate Gradient, Brent-Powell, Hooke-Jeeves) are useful when there is a certain degree of confidence in initial value of the parameters to be optimized.…”

Section: Measurement Setupmentioning

confidence: 99%

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Power management in energy harvesting

Lau¹

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A dual-path wide-power-range rectifier for RF energy harvesting is presented in this thesis. The proposed idea focuses on maximizing efficiency in harvesting energy from the surrounding environment and designated energy source to support wide variety of applications in low power devices' wireless charging. The harvester consists of a low-power rectifier, a high-power rectifier and a voltageaware block. In the low-power rectifier, novel DC-boosted gate bias technique is proposed to enhance power conversion efficiency (PCE) by improving forward peak current, reducing diode forward voltage drop and suppressing reverse leakage current. A novel internal body-biasing technique is proposed in the highpower rectifier to regulate the transistors' threshold voltage (V th ) for optimal efficiency. A voltage-aware block, which consists of a voltage detector, a switch and an adjustable-offset comparator, has been incorporated into the high-power rectification path to minimize overall power consumption.The proposed circuit is fabricated in 65 nm 6M/1P standard CMOS technology.Peak PCE of 70.4% is measured on the low-power rectifier with -5.5 dBm input power at 2.45 GHz when driving a 15 kΩ load. For high-power rectifier, peak PCE of 56.6% is measured with 1.3 dBm input power at 2.45 GHz when driving a 15 kΩ load. The chip has PCE higher than 20% over a 19.8 dB of extended input power range from -13.5 dBm to 6.3 dBm.

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