Design of Reversible Logic Based ALU

Dhanabal, R.; Sahoo, Sarat Kumar; Bharathi, V. Subbiah; Bhavya, V.; Chandrakant, Patil Ashwini; Sarannya, K.

doi:10.1007/978-81-322-2671-0_29

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…Analysis of different adder circuits by implementing ASIC library and FPGA families is tabulated. Comparison of existing multipliers and proposal of a new design for optimized performance [11] may be the next level of development., Implementation of Design of basic building blocks of ALU [9], MAC [15], FPU [14], RNS MAC [13], ALU-DBGU [12], FinFET based design [5], Reversible logic based ALU [6], Floating-Point Fused Multiply-Add Unit [7], Reversible logic based ALU [8] are few design were modified basic blocks can be used as library component for future analysis .…”

Section: Discussionmentioning

confidence: 99%

High Performance Energy Efficient Computation Elements of Processing Unit

Rengasamy,

2019

IJEAT

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in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.

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Section: Discussionmentioning

confidence: 99%

High Performance Energy Efficient Computation Elements of Processing Unit

Rengasamy,

2019

IJEAT

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“…Reversible logic gate-based ALU design was discussed by Dhanabal, R., Sarat Kumar Sahoo, and others [5]. TSG is the first reversible gate that functions as a complete adder.…”

Section: Literature Surveymentioning

confidence: 99%

Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

Dharmavaram,

2024

AEJ

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The compact and accurate way of representing numbers in a wide range is the advantage of floating-point (FP) representation and computation. The floating-point digital signal processors offer the IPs that should have the features of low power, high performance, and less area in cost-effective designs. The proposed paper demonstrates the design and implementation of a 32-bit floating-point arithmetic unit (FPAU). The arithmetic operations performed by the FPAU are in the IEEE 754 single precision format for FP numbers. Before performing the 32-bit FP arithmetic operations, the input operands are converted to IEEE 754 single precision. In order to make use of this functional unit in the processor designs, the proposed work discuss about the creation of custom IP. The validation and verification of this IP will be done with the Xilinx Vivado Design software. Here, the verification is performed with VIO hardware debug IP and Zed board. This FPAU IP can be used in DSP applications and can also be used as a floating-point arithmetic block in semi-custom microprocessor and microcontroller designs.

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“…Some of them [11,18,19,26,31] are focused on direct implementation of the FPA unit using either VHSIC hardware description language or Verilog. Others [4,10,15,20,22,25,33,36] attempted to reduce hardware requirement, thereby improving power consumption and delay.…”

Section: Introductionmentioning

confidence: 99%

The design and implementation of a 16 bit floating point arithmetic unit using BZK.SAU.FPGA microcomputer assembly language

Öztekin

Kisioglu

Gülbağ

et al. 2022

Comp Applic In Engineering

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The microcomputer architecture named BZK.SAU.FPGA, which was developed in 2014, was used to increase efficiency in the teaching of the Computer Architecture and Organization course, which is one of the basic courses of the Department of Computer Engineering. In the last version released in 2018, the architecture has been started to be used in many engineering disciplines with its modular structure and a basic operating system. However, this architecture uses fixed-point numbers in arithmetic operations. Although this situation contributes to its use as an educational tool at the beginner level for new learners, the fact that it cannot operate with floating point numbers is one of the biggest shortcomings of the educational tool. Floating point numbers are used extensively in applications such as mathematical analysis, signal processing, image processing, and so on. Therefore, in this study, the FPA unit for the computation of addition, subtraction, multiplication, and division operations is integrated into this architecture. For FPA unit implementation, an assembly-level program has been embedded in the architecture using an IEEE-754 half-precision binary format (FP16) with the aim of presenting the fundamental of the floating-point computation. The FPA unit proposed to observe the behavior of floating point numbers in arithmetic operations and increase awareness of these issues was used as an auxiliary tool in the computer architecture course. A pre-and postsurvey study was conducted to see the learning outcomes of students using this tool on floating point numbers. We found a significant association between pre-and postsurvey, indicating that students' knowledge about the behavior of floating point numbers increased (p < .001).

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Design of Reversible Logic Based ALU

Cited by 3 publications

References 6 publications

High Performance Energy Efficient Computation Elements of Processing Unit

High Performance Energy Efficient Computation Elements of Processing Unit

Custom Ip Design and Verification for Ieee754 Single Precision Floating Point Arithmetic Unit

The design and implementation of a 16 bit floating point arithmetic unit using BZK.SAU.FPGA microcomputer assembly language

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