2019
DOI: 10.1109/tcsii.2018.2888897
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Design of Power Efficient Variable Bandwidth Non-Maximally Decimated FRM Filters for Wideband Channelizer

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Cited by 17 publications
(6 citation statements)
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“…Fig. 4 shows the comparison of the proposed optimized filter and the prototype filter designed in [21] and [22]. The passband cutoff frequency, stopband start frequency, and order of the three are consistent.…”
Section: A Filter Designmentioning
confidence: 81%
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“…Fig. 4 shows the comparison of the proposed optimized filter and the prototype filter designed in [21] and [22]. The passband cutoff frequency, stopband start frequency, and order of the three are consistent.…”
Section: A Filter Designmentioning
confidence: 81%
“…The prototype filter optimized and designed in this article meets the constraint conditions. Compared with [21] and [22], it has a greater stopband attenuation and a more pronounced trend of steep descent in the transition zone. It is beneficial for reducing the "bulge" phenomenon in the overlapping zone.…”
Section: A Filter Designmentioning
confidence: 99%
See 1 more Smart Citation
“…A drawback of the coefficient decimation based methods is that the passband ripple and stopband attenuation in the resultant frequency response characteristics deteriorates as the value of the decimation factor increases. Interpolation as well as Frequency Response Masking (FRM) [13], [14] techniques developed for obtaining sharp transition width filters without increasing the hardware complexity can also be extended to get a variable bandwidth filter. FRM can be extended to a multistage design as in [15] which is called as fast filter bank.…”
Section: Introductionmentioning
confidence: 99%
“…The frequency-response masking (FRM) technology has attracted much attention due to its great advantages in designing the filter with sharp transition bandwidth (STB) [7]. The combination of the FB and FRM technology makes it possible to improve the performance of a channelised transmitter [8,9]. At the same time, the design of a channelised transmitter structure with low complexity can reduce the hardware resource consumption on field programmable gate array (FPGA) [10,11].…”
Section: Introductionmentioning
confidence: 99%