Design of Power Efficient Analog to Digital Converter

Abstract

Analog to Digital Converters (ADCs) plays a critical role in modern electronic systems, enabling the conversion of continuous analog signals into digital representations which require low power consumption and high conversion efficiency. The demand for low- power electronic devices continue to grow; efficient ADCs play a crucial role in power- sensitive applications. The design and comparative analysis of three distinct ADC architectures, namely Flash, Successive Approximation Register (SAR), and Sub ranging, all implemented in a 180nm Complementary Metal Oxide Semiconductor (CMOS) technology with a focus on achieving low power consumption. The Flash ADC, known for its high-speed conversion in a single step, is examined in terms of power efficiency, especially as it relates to its suitability for high-speed applications. The SAR ADC, characterized by its iterative approximation process, is assessed for its power consumption during precise conversions. Subranging ADCs, combining speed and resolution through multi- stage conversion, are analyzed for their power efficiency and effectiveness in balancing these attributes. The average power of the three ADCs with resolution of 4 bits is compared. From the existing ADC average power is reduced 25% for Flash, 36% for SAR and 34% for Subranging ADC and the most effective architecture is Subranging ADC with an average power of 3.125 mW.