Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA

Dhanabalan, G.; Selvi, S. Tamil

doi:10.1016/j.csi.2014.12.002

Cited by 9 publications

(4 citation statements)

References 9 publications

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“…where, Both the AIM and the AOM must have a processor to ensure proper signal conversion. Thus, the AIM, AOM, and PLC have processors in their architecture [20]. Because the processor executes only one instruction at a time, the PLC has to wait for the AIM to complete its operation.…”

Section: Fpga Design Of Pid Controllermentioning

confidence: 99%

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Dhanabalan¹,

Selvi²,

Mahdal

2022

Sensors

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A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

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Section: Fpga Design Of Pid Controllermentioning

confidence: 99%

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Dhanabalan¹,

Selvi²,

Mahdal

2022

Sensors

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“…The problems of data dependency, output dependency can be eliminated by using field programmable gate array (FPGA) to execute LD in terms of Hardware description Language (HDL) code as the execution is parallel and hardware based [8]. The effect of increase in number of digital inputs, number of rungs has zero impact in the execution time.…”

Section: Fig 2 Example Ladder Diagram For Data Dependency and Output ...mentioning

confidence: 99%

“…Table 1 compares the advantages of using FPGA with processor in a process. for concurrent execution [8].…”

Section: Fig 2 Example Ladder Diagram For Data Dependency and Output ...mentioning

confidence: 99%

Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Dhanabalan

Selvi²

2022

Wireless Pers Commun

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Powerful advantages of programmable logic controller (PLC) dominate process industries. Scan time of PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed applications. PLC executes the instructions represented through LD. PLC programmers are not familiar with FPGA programming. But, FPGA does not support LD based programming. This work has developed application software to generate equivalent VerilogHDL code for LD using LabVIEW. Novelty in this work is that each rung is defined using an "assign" statement which helps simultaneous execution of all the rungs. A data acquisition system was created to monitor the digital signals handled by the FPGA. The software was verified with a case study of substances mixing and traffic light control system.

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“…Along these lines, the issue of thinking of advanced filters with the minimum area and low‐power utilization has gotten a decent consideration all through the most recent decade. Advantages of using FPGA are its concurrent execution; propagation delay of the logic implemented in the FPGA is the delay of the design …”

Section: Introductionmentioning

confidence: 99%

Implementation of FIR filter using reversible modified carry select adder

Sekar

Sasipriya²

2018

Concurrency and Computation

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Summary Any arithmetic operation can be performed using the method of Reversible process which allows minimum arithmetic execution. An essential scenario for achieving this condition is the arithmetic design connections should be of one to one. The Finite Impulse Response (FIR) Filter is that the indispensable part to design digital signal processing framework. The adders and multipliers assume an urgent part in FIR filter while thinking about the power. In this paper, an effective FIR filter is actualized utilizing minimum power reversible modified SQRT carry select adder utilizing Brent Kung adder and D latch. Reversible logic has developed as another outline method to the customary rationale, prompting low power consumption and lesser circuit region. For accomplishing low power, reversible rationale method of task is implemented inside the style. The proposed configuration accomplishes three‐overlap benefits in terms of Area‐power‐delay. From the combination comes about, the newly portrayed minimum power FIR filter configuration shows low power of 294641.397 nW when contrasted with regular outline. Proposed FIR Filter is reenacted by utilizing rhythm device as cadence tool.

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Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA

Cited by 9 publications

References 9 publications

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Implementation of FIR filter using reversible modified carry select adder

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