Design of Optimized Radix-4 FFT Processor with Multiplier Sharing Method

Abstract

To implement the parallel pipelined FFT architecture in OFDM applications. The OFDM has developed in wide band Digital communication. The radix4 algorithm can achieve to reduce the half computational steps compare than the radix2 algorithm and R4MDC is reduces the slices and power consumption than the single path delay feedback. It can be converted into real and imaginary values. To reduce the twiddle factor complexity by using the bit parallel multiplier. It can be exploits the constant twiddle factor when the twiddle factor multiplicatier relocate the twiddle factor multiplications in timing process. The changes can be appeared in multiplications so have to perform the TF at clock signals in two ways data path.