Design of Many-Core Big Little µBrains for Energy-Efficient Embedded Neuromorphic Computing

Varshika, M. Lakshmi; Balaji, Adarsha; Corradi, Federico; Das, Anup; Stuijt, Jan; Catthoor, Francky

doi:10.23919/date54114.2022.9774613

Cited by 16 publications

(12 citation statements)

References 25 publications

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“…Figure 4 shows the architecture of a many-core neuromorphic hardware (left sub-figure). We take the example of two recent designs -DYNAPs [5], where each core consists of an N ×N crossbar with 𝑁 pre-synaptic neurons connected to 𝑁 post-synaptic neurons (middle sub-figure), and 𝜇Brain [18], where each core consists of neurons that are organized in three layers with 𝑁 neurons in layer 1, 𝑀 neurons in layer 2, and 𝑃 neurons in layer 3 (right sub-figure).…”

Section: Proposed Design Methodology 31 Novel Hardware With Astrocyte...mentioning

confidence: 99%

“…A 128 × 128 crossbar core consists of 128 input and 128 output neurons, while a 𝜇Brain core consists of 256 neurons in layer 1, 64 neurons in layer 2, and 16 neurons in layer 3. We use a distance-based heuristic [18] to partition an inference model into clusters, where each cluster can be implemented on a core of the hardware. 1 It sorts all neurons of a model based on their distances from output neurons.…”

Section: Software Mapping Frameworkmentioning

confidence: 99%

“…The power consumption of an astrocyte design is shown in Figure 6, distributed into clocks, signals, logic, DSP, BRAM, MMCM, and I/O. Table 1: Implementation of an astrocyte and the baseline 𝜇Brain [18] and crossbar [5] designs on Xilinx VCU128.…”

Section: Astrocyte Area and Powermentioning

confidence: 99%

“…2) redundant mapping technique [20], and 3) the proposed design methodology. Design areas are reported for both the 𝜇Brain-based core [18] and the crossbar-based core [5]. All results are normalized to the 𝜇Brain-based design implementing the LeNet model using the model replication technique.…”

Section: Model Areamentioning

confidence: 99%

“…Modern embedded systems are embracing neuromorphic devices to implement spiking-based deep learning inference applications [3]. A neuromorphic device is designed as a many-core hardware, where each core consists of silicon circuitries to implement neurons and synapses [18]. Although technology scaling has provided a steady increase of performance, increased power densities (hence temperatures) and other scaling effects create an adverse impact on the reliability by increasing the likelihood of transient, intermittent, and permanent faults in the neuron and synapse circuitries [13,14].…”

Section: Introductionmentioning

confidence: 99%

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A design methodology for fault-tolerant computing using astrocyte neural networks

Isik

Paul

Varshika

et al. 2022

Proceedings of the 19th ACM International Conference on Computing Frontiers

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We propose a design methodology to facilitate fault tolerance of deep learning models. First, we implement a many-core fault-tolerant neuromorphic hardware design, where neuron and synapse circuitries in each neuromorphic core are enclosed with astrocyte circuitries, the star-shaped glial cells of the brain that facilitate selfrepair by restoring the spike firing frequency of a failed neuron using a closed-loop retrograde feedback signal. Next, we introduce astrocytes in a deep learning model to achieve the required degree of tolerance to hardware faults. Finally, we use a system software to partition the astrocyte-enabled model into clusters and implement them on the proposed fault-tolerant neuromorphic design. We evaluate this design methodology using seven deep learning inference models and show that it is both area-and power-efficient. CCS CONCEPTS• Hardware → Neural systems; • Computer systems organization → Dependable and fault-tolerant systems and networks.

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Section: Proposed Design Methodology 31 Novel Hardware With Astrocyte...mentioning

confidence: 99%

Section: Software Mapping Frameworkmentioning

confidence: 99%