Design of low-voltage front-end interface for switched-op amp circuits

Karthikeyan, S. Prabhakar; Tamminneedi, A.; Boecker, Charlie; Lee, E.K.F.

doi:10.1109/82.958342

Cited by 12 publications

(4 citation statements)

References 6 publications

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“…Another problem to be faced with by the switched-ampop technique is the need for an input switch in most circuits, so that a front-end interface must be added. Some solutions can be found in [23,24]. Still, more complexity is added.…”

Section: Introductionmentioning

confidence: 99%

A Switched-MOSFET Programmable Low-Voltage Filter

Marques¹,

Serdijn²

2020

JICS

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This paper describes a digitally programmable low-voltage low-power analogue filter that can be used in hearing-aid circuits. The filter employs the recently introduced switched-MOSFET technique, a sampled-data technique suitable for low supply voltage operation since it avoids the conduction gap of the switches and does not need any dedicated process. The filter was implemented using the DIMES 1.6μm CMOS process and achieves 64 dB dynamic range. The total current consumption, drawn from a 2.2V supply, equals 93μA.

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Section: Introductionmentioning

confidence: 99%

A Switched-MOSFET Programmable Low-Voltage Filter

Marques¹,

Serdijn²

2020

JICS

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“…The number of the utilized ADCs is equal to the number of recording channels or several ADCs are shared between all channels to minimize the chip area . However, the SAR ADC has stringent requirements in the reference buffer and front‐end circuits resulting in more power consumption …”

Section: Introductionmentioning

confidence: 99%

“…3,4 However, the SAR ADC has stringent requirements in the reference buffer and front-end circuits resulting in more power consumption. 5 Recently, the incremental sigma-delta (IΣΔ) ADC is utilized in the neural recording implants. 6,7 There is a one-toone mapping between the input and output samples in IΣΔ ADCS because of the resetting in the modulator and decimation filter.…”

Section: Introductionmentioning

confidence: 99%

An adaptive continuous‐time incremental Σ∆ ADC for neural recording implants

Barati

Yavari

2018

Circuit Theory & Apps

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Summary In this paper, an analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous‐time (CT) incremental sigma‐delta (IΣ∆) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B‐noise) with 8‐bit and 3‐bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B‐noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit‐level implementation of the CT IΣ∆ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90‐nm complementary metal‐oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.

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“…Input structures utilizing a transimpedance amplifier instead of an opamp have recently been studied in [206]. These circuits have potential for somewhat larger bandwidths than opamp-based circuits.…”

Section: Active Input Structuresmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Design of low-voltage front-end interface for switched-op amp circuits

Cited by 12 publications

References 6 publications

A Switched-MOSFET Programmable Low-Voltage Filter

A Switched-MOSFET Programmable Low-Voltage Filter

An adaptive continuous‐time incremental Σ∆ ADC for neural recording implants

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

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