Design of Low Power SRAM using Hierarchical Divided Bit-line Approach in 180-nm Technology

Abstract

Fast low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessors, where the on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory. Simultaneously, power dissipation has become an important consideration both due to the increased integration and operating speeds. Thus, a significant effort has been invested in reducing the power of CMOS RAM chips using circuit and architectural techniques. This paper presents a design using hierarchical divided bit-line approach for reducing active power in SRAMs by 40-50% and access time at the expense of 5-10% increase in the number of transistors when compared to Conventional SRAM. A Hierarchical divided bit line approach is chosen to implement a 1Kb SRAM memory on 0.18 micron CMOS technology using CADENCE design tool.