Design of Low Power On-chip Processor Arrays

Abstract

In this paper, we present an ultra low power design for a class of massively parallel architectures, called tightly-coupled processor arrays. Here, the key idea is to exploit the benefits of a decentralized resource management as inherent to invasive computing for power saving. We propose concepts and studying different architecture trade-offs for hierarchical power management by temporarily shutting down regions of processors through power gating. Moreover, a) overall system chip energy consumption, b) hardware cost, and c) timing overheads are compared for different sizes of power domains. Experimental results show that up to 70 % of system energy consumption may be saved for selected characteristical algorithms and different resource utilizations.

Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs)

“…Thus a tight coupling, cycle-based communcation by point-to-point connections among PEs (from neighbour to neighbour) is realized. Individual PEs do not have direct global memory access (Lari et al, 2012): Data transfer is realized to and from the array through the border PEs that have a connection to the banks of the surrounding memory buffers. The number of invaded PEs can be dynamically reduced and increased depending on the requirements of the corresponding application with different invasion strategies (Muddasani et al, 2012).…”

“…Those individual PE blocks are placed next to each other to form the desired PE array. Possible invasion strategies are linear, meander walk, rectangular and random fashion as explained in Lari et al (2012). It is assumed that each PE is either used (constant power consumption) or not used (just very small leakage power consumption).…”