Design of low power multiplier using reversible logic gate

Thakre, Ashish K.; Chiwande, Sujata S.; Chafale, Sumit D.

doi:10.1109/icgccee.2014.6922303

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Cited by 8 publications

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“…A reversible gate is represented by 'n * n' which indicates it has 'n' inputs and 'n' outputs. There is a one to one mapping between the inputs and outputs of a reversible gate [9], [10]. Most notable reversible gates are Fredkin, Toffoli and Peres [11].…”

Section: Introductionmentioning

confidence: 99%

Low Power 32 x 32 – bit Reversible Vedic Multiplier

Eshack¹,

Krishnakumar²

2019

IJITEE

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Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

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Section: Introductionmentioning

confidence: 99%