Design of Low Power Comparator Using DG Gate

Abstract

In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V + gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis

“…Extensive articles on reversible comparators have been presented by many researchers. However, in this paper, we propose an optimal design of the reversible comparator relative to the circuit presented in [2], based on [20], and describes its QCA implementation. In the reference [2], a comparator design, based on TR and FG gates, is presented; it is a design with a quantum cost of 9, which is a lower quantum cost than similar works.…”

“…Figure 7 shows the quantum implementation of this gate. The quantum cost of this gate is equal to 1 [20]. Table 2 also shows the truth table of this gate.…”